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Fri, 20 Mar 2026 17:33:44 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9745.007; Fri, 20 Mar 2026 17:33:43 +0000 Message-ID: <0231b5bc-03f0-4207-b0c4-fb6daf19d135@nvidia.com> Date: Fri, 20 Mar 2026 13:33:40 -0400 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 06/10] gpu: nova-core: convert PDISP registers to kernel register macro To: Alexandre Courbot , Danilo Krummrich , Alice Ryhl , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Miguel Ojeda , Boqun Feng , Gary Guo , =?UTF-8?Q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross Cc: John Hubbard , Alistair Popple , Timur Tabi , Zhi Wang , Eliot Courtney , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org, rust-for-linux@vger.kernel.org References: <20260320-b4-nova-register-v2-0-88fcf103e8d4@nvidia.com> <20260320-b4-nova-register-v2-6-88fcf103e8d4@nvidia.com> Content-Language: en-US From: Joel Fernandes In-Reply-To: <20260320-b4-nova-register-v2-6-88fcf103e8d4@nvidia.com> Content-Type: text/plain; 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> > if hal.supports_display(bar) { > - match regs::NV_PDISP_VGA_WORKSPACE_BASE::read(bar).vga_workspace_addr() { > + match bar > + .read(regs::NV_PDISP_VGA_WORKSPACE_BASE) > + .vga_workspace_addr() > + { > Some(addr) => { > if addr < base { > const VBIOS_WORKSPACE_SIZE: u64 = usize_as_u64(SZ_128K); > diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs > index 61a8dba22d88..b051d5568cd8 100644 > --- a/drivers/gpu/nova-core/regs.rs > +++ b/drivers/gpu/nova-core/regs.rs > @@ -250,10 +250,14 @@ pub(crate) fn usable_fb_size(self) -> u64 { > > // PDISP > > -register!(NV_PDISP_VGA_WORKSPACE_BASE @ 0x00625f04 { > - 3:3 status_valid as bool, "Set if the `addr` field is valid"; > - 31:8 addr as u32, "VGA workspace base address divided by 0x10000"; > -}); > +io::register! { > + pub(crate) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 { > + /// VGA workspace base address divided by 0x10000. > + 31:8 addr; > + /// Set if the `addr` field is valid. > + 3:3 status_valid => bool; > + } > +} Shouldn't this re-ordering of bit ranges be a separate patch? Also, what did we conclude on the ordering issue? I remember this was discussed, but I am not sure what the conclusion was. Other than that, Reviewed-by: Joel Fernandes -- Joel Fernandes