From: Neil Armstrong <neil.armstrong@linaro.org>
To: Alexander Koskovich <akoskovich@pm.me>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Rob Clark <robin.clark@oss.qualcomm.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org
Subject: Re: [PATCH v3 4/4] drm/msm/dpu: fix video mode DSC INTF timing width calculation
Date: Thu, 19 Mar 2026 15:09:13 +0100 [thread overview]
Message-ID: <1360a31d-669e-48df-a1be-f0af4a253cd7@linaro.org> (raw)
In-Reply-To: <20260319-dsi-rgb101010-support-v3-4-85b99df2d090@pm.me>
Hi,
On 3/19/26 12:58, Alexander Koskovich wrote:
> Using bits_per_component * 3 as the divisor for the compressed INTF
> timing width produces constant FIFO errors for the BOE BF068MWM-TD0
> panel due to bits_per_component being 10 which results in a divisor
> of 30 instead of 24.
>
> Regardless of the compression ratio and pixel depth, 24 bits of
> compressed data are transferred per pclk, so the divisor should
> always be 24.
Not true with widebus, specify why 24 and because DSI widebus is not implemented yet.
>
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index 0ba777bda253..5419ef0be137 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -122,19 +122,18 @@ static void drm_mode_to_intf_timing_params(
> }
>
> /*
> - * for DSI, if compression is enabled, then divide the horizonal active
> - * timing parameters by compression ratio. bits of 3 components(R/G/B)
> - * is compressed into bits of 1 pixel.
> + * For DSI, if DSC is enabled, 24 bits of compressed data are
> + * transferred per pclk regardless of the source pixel depth.
> */
> if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
> struct drm_dsc_config *dsc =
> dpu_encoder_get_dsc_config(phys_enc->parent);
> +
Drop this change
> /*
> * TODO: replace drm_dsc_get_bpp_int with logic to handle
> * fractional part if there is fraction
> */
> - timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /
> - (dsc->bits_per_component * 3);
> + timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / 24;
It would be helpful to somehow show that 24 is 8 * 3, 8 being the byte width and 3 the compression ratio.
> timing->xres = timing->width;
> }
> }
>
next prev parent reply other threads:[~2026-03-19 14:09 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-19 11:57 [PATCH v3 0/4] drm/msm: add RGB101010 pixel format and fix 10-bit DSC timing Alexander Koskovich
2026-03-19 11:57 ` [PATCH v3 1/4] drm/msm/dsi: rename MSM8998 DSI version from V2_2_0 to V2_0_0 Alexander Koskovich
2026-03-19 12:05 ` Konrad Dybcio
2026-03-19 18:50 ` Dmitry Baryshkov
2026-03-21 18:21 ` Claude review: " Claude Code Review Bot
2026-03-19 11:57 ` [PATCH v3 2/4] drm/msm/dsi: add DSI version >= comparison helper Alexander Koskovich
2026-03-19 12:08 ` Konrad Dybcio
2026-03-19 18:50 ` Dmitry Baryshkov
2026-03-19 18:54 ` Dmitry Baryshkov
2026-03-21 18:21 ` Claude review: " Claude Code Review Bot
2026-03-19 11:57 ` [PATCH v3 3/4] drm/msm/dsi: Add support for RGB101010 pixel format Alexander Koskovich
2026-03-19 12:12 ` Konrad Dybcio
2026-03-19 18:59 ` Dmitry Baryshkov
2026-03-19 19:03 ` Alexander Koskovich
2026-03-20 9:22 ` kernel test robot
2026-03-20 17:58 ` kernel test robot
2026-03-21 18:21 ` Claude review: " Claude Code Review Bot
2026-03-19 11:58 ` [PATCH v3 4/4] drm/msm/dpu: fix video mode DSC INTF timing width calculation Alexander Koskovich
2026-03-19 14:09 ` Neil Armstrong [this message]
2026-03-19 14:40 ` Alexander Koskovich
2026-03-19 14:54 ` Neil Armstrong
2026-03-19 17:23 ` Jonathan Marek
2026-03-19 17:31 ` Alexander Koskovich
2026-03-19 19:02 ` Jonathan Marek
2026-03-20 1:45 ` Dmitry Baryshkov
2026-03-20 3:55 ` Alexander Koskovich
2026-03-20 4:25 ` Jonathan Marek
2026-03-20 4:46 ` Alexander Koskovich
2026-03-20 6:38 ` Dmitry Baryshkov
2026-03-20 6:50 ` Alexander Koskovich
2026-03-20 7:02 ` Alexander Koskovich
2026-03-20 7:36 ` Dmitry Baryshkov
2026-03-20 7:47 ` Alexander Koskovich
2026-03-20 8:17 ` Alexander Koskovich
2026-03-20 7:02 ` Dmitry Baryshkov
2026-03-20 7:34 ` Dmitry Baryshkov
2026-03-19 19:05 ` Dmitry Baryshkov
2026-03-21 18:21 ` Claude review: " Claude Code Review Bot
2026-03-21 18:21 ` Claude review: drm/msm: add RGB101010 pixel format and fix 10-bit DSC timing Claude Code Review Bot
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