* RE: [PATCH] drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes
2025-07-02 22:39 [PATCH] drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes Khaled Almahallawy
@ 2025-07-07 13:51 ` Cavitt, Jonathan
2026-03-13 5:00 ` [PATCH v2] " Khaled Almahallawy
2026-03-13 21:29 ` Claude review: " Claude Code Review Bot
2 siblings, 0 replies; 4+ messages in thread
From: Cavitt, Jonathan @ 2025-07-07 13:51 UTC (permalink / raw)
To: Almahallawy, Khaled, dri-devel@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Shankar, Uma, Sean Paul, Nikula, Jani, Cavitt, Jonathan
-----Original Message-----
From: Almahallawy, Khaled <khaled.almahallawy@intel.com>
Sent: Wednesday, July 2, 2025 3:39 PM
To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
Cc: Almahallawy, Khaled <khaled.almahallawy@intel.com>; Shankar, Uma <uma.shankar@intel.com>; Sean Paul <seanpaul@chromium.org>; Cavitt, Jonathan <jonathan.cavitt@intel.com>; Nikula, Jani <jani.nikula@intel.com>
Subject: [PATCH] drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes
>
> Several Link Layer tests (4.2.2.1-2, 4.2.2.7-9) fail because DPTX doesn't
> read DPCD ADAPTER_CAP addresses (0x000F and 0x220F).
>
> 4.2.2.1 test states [1]:
> "Fail1: Source DUT failed to read the DPCD Receiver Capability field
> (DPCD:00000h:0000Fh) through AUX_CH before link training."
>
> 4.2.2.2 test states [1]:
> "Fail2: Source DUT failed to read the DPCD Extended Receiver Capability
> field (DPCD:02200h:0220Fh) through AUX_CH before link training."
>
> Additionally, the spec [2] states:
> "The Source device shall respond to Hot Plug event/Hot Re-plug event by
> first reading DPCD Link/Sink Device Status registers at DPCD 00200h
> through 00205h -or- DPCD 02002h through 0200Fh. If the link is unstable
> or lost, the Source device then reads the DPCD Receiver Capabilities
> registers at DPCD 00000h through 0000Fh to determine the appropriate
> information needed to train the link. The Source device shall then
> initiate link training."
>
> Increasing DP_RECEIVER_CAP_SIZE by 1 byte ensures passing the test
> conditions for these link layer tests.
>
> [1]: DisplayPort v2.1 Link Layer Compliance Test Specification
> sections 4.2.2.1 & 4.2.2.2
> [2]: DisplayPort Standard v2.1 - Sec 5.1.4 Source Device Behavior
> upon HPD Pulse Detection
>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
LGTM.
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
-Jonathan Cavitt
> ---
> include/drm/display/drm_dp.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 811e9238a77c..960c9757ba76 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -1681,7 +1681,7 @@ enum drm_dp_phy {
> #define DP_LINK_STATUS_SIZE 6
>
> #define DP_BRANCH_OUI_HEADER_SIZE 0xc
> -#define DP_RECEIVER_CAP_SIZE 0xf
> +#define DP_RECEIVER_CAP_SIZE 0x10
> #define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
> #define EDP_PSR_RECEIVER_CAP_SIZE 2
> #define EDP_DISPLAY_CTL_CAP_SIZE 5
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v2] drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes
2025-07-02 22:39 [PATCH] drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes Khaled Almahallawy
2025-07-07 13:51 ` Cavitt, Jonathan
@ 2026-03-13 5:00 ` Khaled Almahallawy
2026-03-13 21:29 ` Claude review: " Claude Code Review Bot
2 siblings, 0 replies; 4+ messages in thread
From: Khaled Almahallawy @ 2026-03-13 5:00 UTC (permalink / raw)
To: dri-devel
Cc: intel-gfx, intel-xe, Khaled Almahallawy, Uma Shankar,
Jonathan Cavitt, Jani Nikula
Several Link Layer tests (4.2.2.1-2, 4.2.2.7-9) fail because DPTX doesn't
read DPCD ADAPTER_CAP addresses (0x000F and 0x220F).
4.2.2.1 test states [1]:
"Fail1: Source DUT failed to read the DPCD Receiver Capability field
(DPCD:00000h:0000Fh) through AUX_CH before link training."
4.2.2.2 test states [1]:
"Fail2: Source DUT failed to read the DPCD Extended Receiver Capability
field (DPCD:02200h:0220Fh) through AUX_CH before link training."
Additionally, the spec [2] states:
"The Source device shall respond to Hot Plug event/Hot Re-plug event by
first reading DPCD Link/Sink Device Status registers at DPCD 00200h
through 00205h –or– DPCD 02002h through 0200Fh. If the link is unstable
or lost, the Source device then reads the DPCD Receiver Capabilities
registers at DPCD 00000h through 0000Fh to determine the appropriate
information needed to train the link. The Source device shall then
initiate link training."
Increasing DP_RECEIVER_CAP_SIZE by 1 byte ensures passing the test
conditions for these link layer tests.
[1]: DisplayPort v2.1 Link Layer Compliance Test Specification
sections 4.2.2.1 & 4.2.2.2
[2]: DisplayPort Standard v2.1 - Sec 5.1.4 Source Device Behavior
upon HPD Pulse Detection
v2: Rebase
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
---
include/drm/display/drm_dp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 8b15d3eeb716..6512883647ce 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1688,7 +1688,7 @@ enum drm_dp_phy {
#define DP_LINK_STATUS_SIZE 6
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
-#define DP_RECEIVER_CAP_SIZE 0xf
+#define DP_RECEIVER_CAP_SIZE 0x10
#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
#define DP_DSC_BRANCH_CAP_SIZE 3
#define EDP_PSR_RECEIVER_CAP_SIZE 2
--
2.43.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* Claude review: drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes
2025-07-02 22:39 [PATCH] drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes Khaled Almahallawy
2025-07-07 13:51 ` Cavitt, Jonathan
2026-03-13 5:00 ` [PATCH v2] " Khaled Almahallawy
@ 2026-03-13 21:29 ` Claude Code Review Bot
2 siblings, 0 replies; 4+ messages in thread
From: Claude Code Review Bot @ 2026-03-13 21:29 UTC (permalink / raw)
To: dri-devel-reviews
Overall Series Review
Subject: drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes
Author: Khaled Almahallawy <khaled.almahallawy@intel.com>
Patches: 3
Reviewed: 2026-03-14T07:29:32.912351
---
This is a single-patch series (v2 is a rebase of v1) that fixes `DP_RECEIVER_CAP_SIZE` from 0xf (15 bytes) to 0x10 (16 bytes) to include the `DP_ADAPTER_CAP` register at DPCD address 0x00F. The change is well-motivated by the DP 2.1 spec and compliance test failures.
The fix is **correct and well-justified**. The DP spec clearly defines the Receiver Capability field as DPCD addresses 0x00000h through 0x0000Fh (inclusive), which is 16 bytes. The current value of 0xf (15) misses the last byte (`DP_ADAPTER_CAP`). Notably, AMD's DC driver already works around this by hardcoding `uint8_t dpcd_data[16]` with a comment referencing `DP_ADAPTER_CAP` (`link_dp_capability.c:1740-1743`), which independently confirms this was a known deficiency.
**Impact assessment**: `DP_RECEIVER_CAP_SIZE` is used extensively across the kernel — in struct field declarations (i915, nouveau, radeon, amdgpu, MSM, MediaTek, various bridges), local arrays, function signatures, and AUX read lengths. All of these will grow by 1 byte. This is benign:
- Local arrays and struct fields grow by 1 byte — no ABI concern for userspace.
- The nouveau `nvif_outp_dp_train_v0` struct embeds `dpcd[DP_RECEIVER_CAP_SIZE]`, but this is an internal kernel interface (not UAPI), so the size change is safe.
- `drm_dp_read_extended_dpcd_caps()` will also correctly read one additional byte from the 0x2200 range (through 0x220F), which is exactly what compliance test 4.2.2.2 requires.
**Risk**: Low. The extra byte read is harmless — all DP sinks must implement this register range per the spec.
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 4+ messages in thread