[PATCH 00/14] var-som-6ul: improve support for variants

[PATCH 00/14] var-som-6ul: improve support for variants

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Hello,
this patch series improves support for Variscite VAR-SOM-6UL based boards.

The first two patches fix DT/dmesg warnings.

Then add support for the imx6ull CPU variant of the VAR-SOM-6UL.

Then improves/fixes the following features/options that are currently not
working on the concerto EVK board:
  - ethernet ports ENET1
  - LVDS display panel
  - Wifi/Bt

Also factor out optional features into separate DTSI include files, so it will be
easier to support them for other boards, and to make sure they are not
unconditionnally enabled.

I have tested these changes on a Variscite concerto EVK board using a
VAR-SOM-6UL with the following options:
  - EC (ethernet phy on SOM)
  - LD (LVDS encoder assembled on SOM)
  - WBD (Wi-Fi 802.11 ac/a/b/g/n and Bluetooth 5.2/BLE on SOM)
Result of tests:
  - Both ethernet ports Ok
  - LVDS display panel Ok
  - Wifi/Bt Ok

Also tested on a custom board with a VAR-SOM-6UL SOM (will be submitted in
a future series).

Thank you.

Hugo Villeneuve (14):
  ARM: dts: imx6ul-var-som: fix warning for non-existent dc-supply
    property
  ARM: dts: imx6ul-var-som: fix warning for boolean property with a
    value
  ARM: dts: imx6ul-var-som: change incorrect VAR-SOM-6UL model name
  dt-bindings: arm: fsl: change incorrect VAR-SOM-6UL model name
  dt-bindings: arm: fsl: add variscite,var-som-imx6ull
  ARM: dts: imx6ul-var-som: Factor out common parts for all CPU variants
  ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU
    variants
  ARM: dts: imx6ul-var-som: factor out SD card support
  ARM: dts: imx6ul-var-som: add proper Wifi and Bluetooth support
  ARM: dts: imx6ul-var-som: factor out ENET2 ethernet support
  ARM: dts: imx6ul-var-som: add support for EC configuration option
    (ENET1)
  ARM: dts: imx6ul-var-som: factor out audio support
  dt-bindings: display/lvds-codec: add ti,sn65lvds93
  ARM: dts: imx6ul-var-som: add support for LVDS display panel

 .../devicetree/bindings/arm/fsl.yaml          |   8 +-
 .../bindings/display/bridge/lvds-codec.yaml   |   1 +
 arch/arm/boot/dts/nxp/imx/Makefile            |   3 +
 .../dts/nxp/imx/imx6ul-var-som-audio.dtsi     |  30 ++
 ...ar-som.dtsi => imx6ul-var-som-common.dtsi} | 140 +++-----
 ...ts => imx6ul-var-som-concerto-common.dtsi} | 159 ++-------
 .../nxp/imx/imx6ul-var-som-concerto-full.dts  |  22 ++
 .../dts/nxp/imx/imx6ul-var-som-concerto.dts   | 318 +-----------------
 .../dts/nxp/imx/imx6ul-var-som-enet1.dtsi     |  44 +++
 .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi     |  79 +++++
 .../nxp/imx/imx6ul-var-som-lvds-panel.dtsi    | 112 ++++++
 .../boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi   |  27 ++
 .../boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi |  75 +++++
 arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 219 +-----------
 .../nxp/imx/imx6ull-var-som-concerto-full.dts |  22 ++
 .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |  21 ++
 .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi |  36 ++
 17 files changed, 575 insertions(+), 741 deletions(-)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi
 copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som.dtsi => imx6ul-var-som-common.dtsi} (60%)
 copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som-concerto.dts => imx6ul-var-som-concerto-common.dtsi} (51%)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi


base-commit: 11439c4635edd669ae435eec308f4ab8a0804808
-- 
2.47.3

[PATCH 01/14] ARM: dts: imx6ul-var-som: fix warning for non-existent dc-supply property

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

The dc-supply property is non-existent in Linux now, nor when this DTS file
was created when importing it from Variscite own kernel.

Therefore remove it to fix this warning:

    imx6ul-var-som-concerto.dtb: cpu@0 (arm,cortex-a7): Unevaluated
    properties are not allowed ('dc-supply' was unexpected)
        from schema $id: http://devicetree.org/schemas/arm/cpus.yaml

Fixes: 9d6a67d9c7a9 ("ARM: dts: imx6ul: Add Variscite VAR-SOM-MX6UL SoM support")
Cc: stable@kernel.org
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
index 4e536e0252def..3fb5e2fb68777 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
@@ -45,10 +45,6 @@ &clks {
 	assigned-clock-rates = <786432000>;
 };
 
-&cpu0 {
-	dc-supply = <&reg_gpio_dvfs>;
-};
-
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
-- 
2.47.3

[PATCH 02/14] ARM: dts: imx6ul-var-som: fix warning for boolean property with a value

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

dmesg warning:

  OF: /soc/bus@2000000/ethernet@20b4000/mdio/ethernet-phy@3: Read of
      boolean property 'micrel,rmii-reference-clock-select-25-mhz' with a
      value.

Using of_property_read_bool() for non-boolean properties is deprecated and
results in a warning during runtime since commit c141ecc3cecd
("of: Warn when of_property_read_bool() is used on non-boolean properties")

micrel,rmii-reference-clock-select-25-mhz is a boolean property and should
not have a value, so remove it.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts | 2 +-
 arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi         | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
index 9ff3b374a2b31..085985356668f 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
@@ -79,7 +79,7 @@ ethphy1: ethernet-phy@3 {
 			reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <100000>;
 			micrel,led-mode = <0>;
-			micrel,rmii-reference-clock-select-25-mhz = <1>;
+			micrel,rmii-reference-clock-select-25-mhz;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
index 3fb5e2fb68777..30032be6fdd50 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
@@ -64,7 +64,7 @@ ethphy0: ethernet-phy@1 {
 			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <100000>;
 			micrel,led-mode = <1>;
-			micrel,rmii-reference-clock-select-25-mhz = <1>;
+			micrel,rmii-reference-clock-select-25-mhz;
 		};
 	};
 };
-- 
2.47.3

[PATCH 03/14] ARM: dts: imx6ul-var-som: change incorrect VAR-SOM-6UL model name

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

There is no Variscite module named VAR-SOM-MX6UL.

The official name from the manufacturer is VAR-SOM-6UL.

Change SOM model name to VAR-SOM-6UL to reduce confusion.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts | 4 ++--
 arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi         | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
index 085985356668f..d16e75164fd18 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL
+ * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
  * Variscite SoM mounted on it
  *
  * Copyright 2019 Variscite Ltd.
@@ -11,7 +11,7 @@
 #include <dt-bindings/leds/common.h>
 
 / {
-	model = "Variscite VAR-SOM-MX6UL Concerto Board";
+	model = "Variscite VAR-SOM-6UL Concerto Board";
 	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
 
 	chosen {
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
index 30032be6fdd50..7259526e2b884 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Support for Variscite VAR-SOM-MX6UL Module
+ * Support for Variscite VAR-SOM-6UL Module
  *
  * Copyright 2019 Variscite Ltd.
  * Copyright 2025 Bootlin
@@ -13,7 +13,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-	model = "Variscite VAR-SOM-MX6UL module";
+	model = "Variscite VAR-SOM-6UL module";
 	compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
 
 	memory@80000000 {
-- 
2.47.3

[PATCH 04/14] dt-bindings: arm: fsl: change incorrect VAR-SOM-6UL model name

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

There is no Variscite module named VAR-SOM-MX6UL.

The official name from the manufacturer is VAR-SOM-6UL.

Change SOM model name to VAR-SOM-6UL to reduce confusion.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 5716d701292cf..99dc1b3f1ba92 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -688,7 +688,7 @@ properties:
           - const: phytec,imx6ul-pcl063   # PHYTEC phyCORE-i.MX 6UL
           - const: fsl,imx6ul
 
-      - description: i.MX6UL Variscite VAR-SOM-MX6 Boards
+      - description: i.MX6UL Variscite VAR-SOM-6UL Boards
         items:
           - const: variscite,mx6ulconcerto
           - const: variscite,var-som-imx6ul
-- 
2.47.3

[PATCH 05/14] dt-bindings: arm: fsl: add variscite,var-som-imx6ull

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Add support for the imx6ull CPU variant of the Variscite concerto
board evaluation kit with a VAR-SOM-6UL.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 99dc1b3f1ba92..61cda40d31873 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -797,6 +797,12 @@ properties:
           - const: phytec,imx6ull-pcl063        # PHYTEC phyCORE-i.MX 6ULL
           - const: fsl,imx6ull
 
+      - description: i.MX6ULL Variscite VAR-SOM-6UL Boards
+        items:
+          - const: variscite,mx6ullconcerto  # Variscite VAR-SOM-6UL dev kit board
+          - const: variscite,var-som-imx6ull # Variscite VAR-SOM-6UL SoM (6ULL variant)
+          - const: fsl,imx6ull
+
       - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
         items:
           - enum:
-- 
2.47.3

[PATCH 06/14] ARM: dts: imx6ul-var-som: Factor out common parts for all CPU variants

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Factor out the parts on the Variscite VAR-SOM-6UL [1] that are common to
all CPU variants (6UL, 6ULL, etc).

This will simplify adding future dedicated device tree files for each CPU
variant.

Link: https://www.variscite.com/product/system-on-module-som/cortex-a7/var-som-6ul-nxp-imx6ul-6ull-6ulz/ [1]

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 ...ar-som.dtsi => imx6ul-var-som-common.dtsi} |   6 +-
 arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 214 +-----------------
 .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi |  15 ++
 3 files changed, 18 insertions(+), 217 deletions(-)
 copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som.dtsi => imx6ul-var-som-common.dtsi} (98%)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
similarity index 98%
copy from arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
copy to arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
index 7259526e2b884..2072e8ba4d469 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
@@ -1,14 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Support for Variscite VAR-SOM-6UL Module
+ * Support for the common parts shared by all the different CPU options on
+ * Variscite VAR-SOM-6UL Module
  *
  * Copyright 2019 Variscite Ltd.
  * Copyright 2025 Bootlin
  */
 
-/dts-v1/;
-
-#include "imx6ul.dtsi"
 #include <dt-bindings/clock/imx6ul-clock.h>
 #include <dt-bindings/gpio/gpio.h>
 
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
index 7259526e2b884..35a0c0b3603fd 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
@@ -9,221 +9,9 @@
 /dts-v1/;
 
 #include "imx6ul.dtsi"
-#include <dt-bindings/clock/imx6ul-clock.h>
-#include <dt-bindings/gpio/gpio.h>
+#include "imx6ul-var-som-common.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL module";
 	compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x20000000>;
-	};
-
-	reg_gpio_dvfs: reg-gpio-dvfs {
-		compatible = "regulator-gpio";
-		regulator-min-microvolt = <1300000>;
-		regulator-max-microvolt = <1400000>;
-		regulator-name = "gpio_dvfs";
-		regulator-type = "voltage";
-		gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
-		states = <1300000 0x1
-			  1400000 0x0>;
-	};
-
-	rmii_ref_clk: rmii-ref-clk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <25000000>;
-		clock-output-names = "rmii-ref";
-	};
-};
-
-&clks {
-	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
-	assigned-clock-rates = <786432000>;
-};
-
-&fec1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy0>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy0: ethernet-phy@1 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <1>;
-			clocks = <&rmii_ref_clk>;
-			clock-names = "rmii-ref";
-			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <100000>;
-			micrel,led-mode = <1>;
-			micrel,rmii-reference-clock-select-25-mhz;
-		};
-	};
-};
-
-&iomuxc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_hog>;
-
-	pinctrl_enet1: enet1grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
-			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
-			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
-			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
-			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
-			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
-			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
-			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
-		>;
-	};
-
-	pinctrl_enet1_gpio: enet1-gpiogrp {
-		fsl,pins = <
-			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0 /* fec1 reset */
-		>;
-	};
-
-	pinctrl_enet1_mdio: enet1-mdiogrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
-			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
-		>;
-	};
-
-	pinctrl_hog: hoggrp {
-		fsl,pins = <
-			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* BT Enable */
-			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x03029	/* WLAN Enable */
-		>;
-	};
-
-	pinctrl_sai2: sai2grp {
-		fsl,pins = <
-			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
-			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
-			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
-			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
-			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
-		>;
-	};
-
-	pinctrl_tsc: tscgrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
-			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
-			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
-			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
-		>;
-	};
-
-	pinctrl_uart2: uart2grp {
-		fsl,pins = <
-			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
-			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
-			MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS	0x1b0b1
-			MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS	0x1b0b1
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10069
-			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
-			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
-			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
-			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
-			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
-			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x17059
-			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x17059
-			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x17059
-			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x17059
-		>;
-	};
-
-	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100b9
-			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170b9
-			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170b9
-			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170b9
-			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170b9
-			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170b9
-			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170b9
-			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170b9
-			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170b9
-			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170b9
-		>;
-	};
-
-	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100f9
-			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170f9
-			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
-			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
-			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
-			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
-			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170f9
-			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170f9
-			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170f9
-			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170f9
-		>;
-	};
-};
-
-&pxp {
-	status = "okay";
-};
-
-&sai2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_sai2>;
-	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
-			  <&clks IMX6UL_CLK_SAI2>;
-	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
-	assigned-clock-rates = <0>, <12288000>;
-	fsl,sai-mclk-direction-output;
-	status = "okay";
-};
-
-&snvs_poweroff {
-	status = "okay";
-};
-
-&tsc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_tsc>;
-	xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
-	measure-delay-time = <0xffff>;
-	pre-charge-time = <0xfff>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2>;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&usdhc2 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
-	bus-width = <8>;
-	no-1-8-v;
-	non-removable;
-	keep-power-in-suspend;
-	wakeup-source;
-	status = "okay";
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
new file mode 100644
index 0000000000000..ba482a97623b2
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support for Variscite VAR-SOM-6UL module with imx6ull CPU
+ *
+ * Copyright 2019-2024 Variscite Ltd.
+ * Copyright 2026 Dimonoff
+ */
+
+#include "imx6ull.dtsi"
+#include "imx6ul-var-som-common.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-6UL module";
+	compatible = "variscite,var-som-imx6ull", "fsl,imx6ull";
+};
-- 
2.47.3

[PATCH 07/14] ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU variants

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Export common parts to the Variscite VAR-SOM-6UL dtsi so that they can be
reused on other boards.

This will simplify adding future dedicated device tree files for each CPU
variant.

Add i2c1 pinctrl to var-som dtsi pinmux, so that it can be reused by other
boards.

Reorder pinctrl_gpio_leds to respect alphabetical order.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 arch/arm/boot/dts/nxp/imx/Makefile            |   1 +
 .../dts/nxp/imx/imx6ul-var-som-common.dtsi    |   7 +
 ...ts => imx6ul-var-som-concerto-common.dtsi} |  17 +-
 .../dts/nxp/imx/imx6ul-var-som-concerto.dts   | 312 +-----------------
 .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |  17 +
 5 files changed, 33 insertions(+), 321 deletions(-)
 copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som-concerto.dts => imx6ul-var-som-concerto-common.dtsi} (95%)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts

diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
index de4142e8f3ce8..bc534d0fb1412 100644
--- a/arch/arm/boot/dts/nxp/imx/Makefile
+++ b/arch/arm/boot/dts/nxp/imx/Makefile
@@ -376,6 +376,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
 	imx6ull-tarragon-slavext.dtb \
 	imx6ull-tqma6ull2-mba6ulx.dtb \
 	imx6ull-tqma6ull2l-mba6ulx.dtb \
+	imx6ull-var-som-concerto.dtb \
 	imx6ull-uti260b.dtb \
 	imx6ulz-14x14-evk.dtb \
 	imx6ulz-bsh-smm-m2.dtb
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
index 2072e8ba4d469..22b0c4e0725a5 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
@@ -104,6 +104,13 @@ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x03029	/* WLAN Enable */
 		>;
 	};
 
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
+			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
+		>;
+	};
+
 	pinctrl_sai2: sai2grp {
 		fsl,pins = <
 			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
similarity index 95%
copy from arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
copy to arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
index d16e75164fd18..10a23ae104359 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
@@ -1,19 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
- * Variscite SoM mounted on it
+ * Variscite SoM mounted on it, for all CPU variants.
  *
  * Copyright 2019 Variscite Ltd.
  * Copyright 2025 Bootlin
  */
 
-#include "imx6ul-var-som.dtsi"
 #include <dt-bindings/leds/common.h>
 
 / {
-	model = "Variscite VAR-SOM-6UL Concerto Board";
-	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
-
 	chosen {
 		stdout-path = &uart1;
 	};
@@ -144,22 +140,15 @@ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
 		>;
 	};
 
-	pinctrl_gpio_leds: gpio-ledsgrp {
-		fsl,pins = <
-			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
-		>;
-	};
-
 	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
 		fsl,pins = <
 			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
 		>;
 	};
 
-	pinctrl_i2c1: i2c1grp {
+	pinctrl_gpio_leds: gpio-ledsgrp {
 		fsl,pins = <
-			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
-			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
+			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
 		>;
 	};
 
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
index d16e75164fd18..11b45f105b7ad 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
@@ -1,320 +1,18 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
- * Variscite SoM mounted on it
+ * Variscite SoM mounted on it (6UL CPU variant).
  *
  * Copyright 2019 Variscite Ltd.
  * Copyright 2025 Bootlin
  */
 
+/dts-v1/;
+
 #include "imx6ul-var-som.dtsi"
-#include <dt-bindings/leds/common.h>
+#include "imx6ul-var-som-concerto-common.dtsi"
 
 / {
-	model = "Variscite VAR-SOM-6UL Concerto Board";
+	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
 	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
-
-	chosen {
-		stdout-path = &uart1;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
-
-		key-back {
-			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_BACK>;
-		};
-
-		key-wakeup {
-			gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WAKEUP>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_leds>;
-
-		led-0 {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			label = "gpled2";
-			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-		};
-	};
-};
-
-&can1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan1>;
-	status = "okay";
-};
-
-&fec1 {
-	status = "disabled";
-};
-
-&fec2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy1>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy1: ethernet-phy@3 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <3>;
-			clocks = <&rmii_ref_clk>;
-			clock-names = "rmii-ref";
-			reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <100000>;
-			micrel,led-mode = <0>;
-			micrel,rmii-reference-clock-select-25-mhz;
-		};
-	};
-};
-
-&i2c1 {
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	status = "okay";
-
-	rtc@68 {
-		/*
-		 * To actually use this interrupt
-		 * connect pins J14.8 & J14.10 on the Concerto-Board.
-		 */
-		compatible = "dallas,ds1337";
-		reg = <0x68>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_rtc>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
-	};
-};
-
-&iomuxc {
-	pinctrl_enet2: enet2grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
-			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
-			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
-		>;
-	};
-
-	pinctrl_enet2_gpio: enet2-gpiogrp {
-		fsl,pins = <
-			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0 /* fec2 reset */
-		>;
-	};
-
-	pinctrl_enet2_mdio: enet2-mdiogrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
-			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
-		>;
-	};
-
-	pinctrl_flexcan1: flexcan1grp {
-		fsl,pins = <
-			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
-			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
-		>;
-	};
-
-	pinctrl_gpio_key_back: gpio-key-backgrp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
-		>;
-	};
-
-	pinctrl_gpio_leds: gpio-ledsgrp {
-		fsl,pins = <
-			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
-		>;
-	};
-
-	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
-		fsl,pins = <
-			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
-		>;
-	};
-
-	pinctrl_i2c1: i2c1grp {
-		fsl,pins = <
-			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
-			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
-		>;
-	};
-
-	pinctrl_pwm4: pwm4grp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO05__PWM4_OUT		0x110b0
-		>;
-	};
-
-	pinctrl_rtc: rtcgrp {
-		fsl,pins = <
-			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x1b0b0 /* RTC alarm IRQ */
-		>;
-	};
-
-	pinctrl_uart1: uart1grp {
-		fsl,pins = <
-			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
-			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
-		>;
-	};
-
-	pinctrl_uart5: uart5grp {
-		fsl,pins = <
-			MX6UL_PAD_CSI_DATA00__UART5_DCE_TX	0x1b0b1
-			MX6UL_PAD_CSI_DATA01__UART5_DCE_RX	0x1b0b1
-			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
-			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
-		>;
-	};
-
-	pinctrl_usb_otg1_id: usbotg1idgrp {
-		fsl,pins = <
-			MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID	0x17059
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
-			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
-			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
-			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
-			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
-		>;
-	};
-
-	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
-		fsl,pins = <
-			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
-			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
-			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
-			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
-			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
-		>;
-	};
-
-	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
-		fsl,pins = <
-			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
-			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
-			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
-			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
-			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
-		>;
-	};
-
-	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
-		>;
-	};
-
-	pinctrl_wdog: wdoggrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x78b0
-		>;
-	};
-};
-
-&pwm4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm4>;
-	status = "okay";
-};
-
-&snvs_pwrkey {
-	status = "disabled";
-};
-
-&snvs_rtc {
-	status = "disabled";
-};
-
-&tsc {
-	/*
-	 * Conflics with wdog1 ext-reset-output & SD CD pins,
-	 * so we keep it disabled by default.
-	 */
-	status = "disabled";
-};
-
-/* Console UART */
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
-	status = "okay";
-};
-
-/* ttymxc4 UART */
-&uart5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart5>;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&usbotg1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usb_otg1_id>;
-	dr_mode = "otg";
-	disable-over-current;
-	srp-disable;
-	hnp-disable;
-	adp-disable;
-	status = "okay";
-};
-
-&usbotg2 {
-	dr_mode = "host";
-	disable-over-current;
-	status = "okay";
-};
-
-&usdhc1 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
-	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
-	no-1-8-v;
-	keep-power-in-suspend;
-	wakeup-source;
-	status = "okay";
-};
-
-&wdog1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_wdog>;
-	/*
-	 * To actually use ext-reset-output
-	 * connect pins J17.3 & J17.8 on the Concerto-Board
-	 */
-	fsl,ext-reset-output;
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
new file mode 100644
index 0000000000000..7c601af2657d7
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
+ * Variscite SoM mounted on it (6ULL CPU variant).
+ *
+ * Copyright 2026 Dimonoff
+ */
+
+/dts-v1/;
+
+#include "imx6ull-var-som.dtsi"
+#include "imx6ul-var-som-concerto-common.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
+	compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull";
+};
-- 
2.47.3

[PATCH 08/14] ARM: dts: imx6ul-var-som: factor out SD card support

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Move SD support to a separate include, since it cannot be used at the
same time as the Wifi/BT module.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 .../dts/nxp/imx/imx6ul-var-som-common.dtsi    | 33 ++++++++++++
 .../imx/imx6ul-var-som-concerto-common.dtsi   | 51 -------------------
 .../dts/nxp/imx/imx6ul-var-som-concerto.dts   |  1 +
 .../boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi   | 27 ++++++++++
 .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |  1 +
 5 files changed, 62 insertions(+), 51 deletions(-)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
index 22b0c4e0725a5..dd4ecff1eb786 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
@@ -139,6 +139,39 @@ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS	0x1b0b1
 		>;
 	};
 
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
+		>;
+	};
+
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
 			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10069
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
index 10a23ae104359..ea8d9905ce6e7 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
@@ -186,45 +186,6 @@ MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID	0x17059
 		>;
 	};
 
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
-			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
-			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
-			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
-			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
-		>;
-	};
-
-	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
-		fsl,pins = <
-			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
-			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
-			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
-			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
-			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
-		>;
-	};
-
-	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
-		fsl,pins = <
-			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
-			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
-			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
-			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
-			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
-		>;
-	};
-
-	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
-		>;
-	};
-
 	pinctrl_wdog: wdoggrp {
 		fsl,pins = <
 			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x78b0
@@ -286,18 +247,6 @@ &usbotg2 {
 	status = "okay";
 };
 
-&usdhc1 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
-	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
-	no-1-8-v;
-	keep-power-in-suspend;
-	wakeup-source;
-	status = "okay";
-};
-
 &wdog1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_wdog>;
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
index 11b45f105b7ad..85ebac30d7bed 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
@@ -11,6 +11,7 @@
 
 #include "imx6ul-var-som.dtsi"
 #include "imx6ul-var-som-concerto-common.dtsi"
+#include "imx6ul-var-som-sd.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi
new file mode 100644
index 0000000000000..0e6d9b945eb4a
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support optional SD card interface on Variscite VAR-SOM-6UL module.
+ *
+ * Copyright 2019-2024 Variscite Ltd.
+ * Copyright 2026 Dimonoff
+ */
+
+&iomuxc {
+	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
+		>;
+	};
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
+	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	wakeup-source;
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
index 7c601af2657d7..ebf88c3e1addc 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
@@ -10,6 +10,7 @@
 
 #include "imx6ull-var-som.dtsi"
 #include "imx6ul-var-som-concerto-common.dtsi"
+#include "imx6ul-var-som-sd.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
-- 
2.47.3

[PATCH 09/14] ARM: dts: imx6ul-var-som: add proper Wifi and Bluetooth support

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

The existing configuration of the optional Wifi/Bluetooth module was
copied from the original Variscite kernel tree, and requires custom
scripts to properly configure the Wifi/Bluetooth module.

Add proper support for the optional Wifi and Bluetooth configuration on
VAR-SOM-6UL so that it works out of the box, without any custom scripts.

The SD card interface cannot be used if the Wifi/BT module is in use.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 arch/arm/boot/dts/nxp/imx/Makefile            |  2 +
 .../dts/nxp/imx/imx6ul-var-som-common.dtsi    | 18 ++---
 .../nxp/imx/imx6ul-var-som-concerto-full.dts  | 18 +++++
 .../boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi | 75 +++++++++++++++++++
 arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 15 ++++
 .../nxp/imx/imx6ull-var-som-concerto-full.dts | 18 +++++
 .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 15 ++++
 7 files changed, 151 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts

diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
index bc534d0fb1412..c7f24ee63071f 100644
--- a/arch/arm/boot/dts/nxp/imx/Makefile
+++ b/arch/arm/boot/dts/nxp/imx/Makefile
@@ -339,6 +339,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
 	imx6ul-tx6ul-0011.dtb \
 	imx6ul-tx6ul-mainboard.dtb \
 	imx6ul-var-som-concerto.dtb \
+	imx6ul-var-som-concerto-full.dtb \
 	imx6ull-14x14-evk.dtb \
 	imx6ull-colibri-aster.dtb \
 	imx6ull-colibri-emmc-aster.dtb \
@@ -377,6 +378,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
 	imx6ull-tqma6ull2-mba6ulx.dtb \
 	imx6ull-tqma6ull2l-mba6ulx.dtb \
 	imx6ull-var-som-concerto.dtb \
+	imx6ull-var-som-concerto-full.dtb \
 	imx6ull-uti260b.dtb \
 	imx6ulz-14x14-evk.dtb \
 	imx6ulz-bsh-smm-m2.dtb
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
index dd4ecff1eb786..af8c5d2db53d4 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
@@ -19,6 +19,14 @@ memory@80000000 {
 		reg = <0x80000000 0x20000000>;
 	};
 
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
 	reg_gpio_dvfs: reg-gpio-dvfs {
 		compatible = "regulator-gpio";
 		regulator-min-microvolt = <1300000>;
@@ -68,9 +76,6 @@ ethphy0: ethernet-phy@1 {
 };
 
 &iomuxc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_hog>;
-
 	pinctrl_enet1: enet1grp {
 		fsl,pins = <
 			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
@@ -97,13 +102,6 @@ MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
 		>;
 	};
 
-	pinctrl_hog: hoggrp {
-		fsl,pins = <
-			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* BT Enable */
-			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x03029	/* WLAN Enable */
-		>;
-	};
-
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
new file mode 100644
index 0000000000000..519250b31db24
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
+ * Variscite SoM mounted on it (6UL CPU variant).
+ *
+ * Copyright 2026 Dimonoff
+ */
+
+/dts-v1/;
+
+#include "imx6ul-var-som.dtsi"
+#include "imx6ul-var-som-concerto-common.dtsi"
+#include "imx6ul-var-som-wifi.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
+	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
new file mode 100644
index 0000000000000..6d16ff7909dab
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support optional Wifi/Bluetooth on Variscite VAR-SOM-6UL module.
+ *
+ * Copyright 2019-2024 Variscite Ltd.
+ * Copyright 2026 Dimonoff
+ */
+
+/ {
+	reg_sd1_vmmc: regulator_sd1_vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "VMMC1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		startup-delay-us = <10000>;
+	};
+
+	usdhc1_pwrseq: usdhc1-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_brcm_wifi>;
+		reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&iomuxc {
+	pinctrl_32k_clk: 32kclkgrp {
+		/*
+		 * For TP option, an additional oscillator is assembled on the
+		 * SOM to provide 32 kHz to the WiFi module. Without TP option,
+		 * this pin is configured to provide the 32 KHz clock to the
+		 * WiFi module.
+		 */
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT	0x03029
+		>;
+	};
+};
+
+&tsc {
+	status = "disabled";
+};
+
+/* Bluetooth UART */
+&uart2 {
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_brcm_bt>;
+		shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+		vbat-supply = <&reg_3p3v>;
+		vddio-supply = <&reg_3p3v>;
+	};
+};
+
+&usdhc1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_32k_clk>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_32k_clk>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_32k_clk>;
+	no-1-8-v;
+	non-removable;
+	mmc-pwrseq = <&usdhc1_pwrseq>;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm4329-fmac"; /* LWB option: Sterling LWB5 */
+		reg = <1>;
+	};
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
index 35a0c0b3603fd..b4e6a9316dd81 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
@@ -15,3 +15,18 @@ / {
 	model = "Variscite VAR-SOM-6UL module";
 	compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
 };
+
+&iomuxc {
+	pinctrl_brcm_bt: brcm-bt-grp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* BT_REG_ON (BT_EN) */
+		>;
+	};
+
+	pinctrl_brcm_wifi: brcm-wifi-grp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0	/* WL_PWR (WIFI_PWR 5G) */
+			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x1b0b0	/* WL_REG_ON (WIFI_EN) */
+		>;
+	};
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
new file mode 100644
index 0000000000000..7c0e313603630
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
+ * Variscite SoM mounted on it (6ULL CPU variant).
+ *
+ * Copyright 2026 Dimonoff
+ */
+
+/dts-v1/;
+
+#include "imx6ull-var-som.dtsi"
+#include "imx6ul-var-som-concerto-common.dtsi"
+#include "imx6ul-var-som-wifi.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
+	compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
index ba482a97623b2..3067ff6a1bc74 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
@@ -13,3 +13,18 @@ / {
 	model = "Variscite VAR-SOM-6UL module";
 	compatible = "variscite,var-som-imx6ull", "fsl,imx6ull";
 };
+
+&iomuxc {
+	pinctrl_brcm_bt: brcm-bt-grp {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* BT_REG_ON (BT_EN) */
+		>;
+	};
+
+	pinctrl_brcm_wifi: brcm-wifi-grp {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0	/* WL_PWR (WIFI_PWR 5G) */
+			MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x1b0b0	/* WL_REG_ON (WIFI_EN) */
+		>;
+	};
+};
-- 
2.47.3

[PATCH 10/14] ARM: dts: imx6ul-var-som: factor out ENET2 ethernet support

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Not all boards use the ethernet ENET2 port, so factor out this
functionality to a separate DTSI include file.

On the concerto board, this uses the ethernet PHY assembled on it.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 .../dts/nxp/imx/imx6ul-var-som-common.dtsi    |  7 --
 .../imx/imx6ul-var-som-concerto-common.dtsi   | 50 --------------
 .../nxp/imx/imx6ul-var-som-concerto-full.dts  |  1 +
 .../dts/nxp/imx/imx6ul-var-som-concerto.dts   |  1 +
 .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi     | 68 +++++++++++++++++++
 .../nxp/imx/imx6ull-var-som-concerto-full.dts |  1 +
 .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |  1 +
 7 files changed, 72 insertions(+), 57 deletions(-)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
index af8c5d2db53d4..af9b92f7709b4 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
@@ -37,13 +37,6 @@ reg_gpio_dvfs: reg-gpio-dvfs {
 		states = <1300000 0x1
 			  1400000 0x0>;
 	};
-
-	rmii_ref_clk: rmii-ref-clk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <25000000>;
-		clock-output-names = "rmii-ref";
-	};
 };
 
 &clks {
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
index ea8d9905ce6e7..53cf801f39fcd 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
@@ -56,30 +56,6 @@ &fec1 {
 	status = "disabled";
 };
 
-&fec2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy1>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy1: ethernet-phy@3 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <3>;
-			clocks = <&rmii_ref_clk>;
-			clock-names = "rmii-ref";
-			reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <100000>;
-			micrel,led-mode = <0>;
-			micrel,rmii-reference-clock-select-25-mhz;
-		};
-	};
-};
-
 &i2c1 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default";
@@ -101,32 +77,6 @@ rtc@68 {
 };
 
 &iomuxc {
-	pinctrl_enet2: enet2grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
-			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
-			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
-		>;
-	};
-
-	pinctrl_enet2_gpio: enet2-gpiogrp {
-		fsl,pins = <
-			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0 /* fec2 reset */
-		>;
-	};
-
-	pinctrl_enet2_mdio: enet2-mdiogrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
-			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
-		>;
-	};
-
 	pinctrl_flexcan1: flexcan1grp {
 		fsl,pins = <
 			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
index 519250b31db24..3905171b47b32 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
@@ -11,6 +11,7 @@
 #include "imx6ul-var-som.dtsi"
 #include "imx6ul-var-som-concerto-common.dtsi"
 #include "imx6ul-var-som-wifi.dtsi"
+#include "imx6ul-var-som-enet2.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
index 85ebac30d7bed..d0adcd0e80833 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
@@ -12,6 +12,7 @@
 #include "imx6ul-var-som.dtsi"
 #include "imx6ul-var-som-concerto-common.dtsi"
 #include "imx6ul-var-som-sd.dtsi"
+#include "imx6ul-var-som-enet2.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
new file mode 100644
index 0000000000000..334ed3bbe02ce
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Ethernet ENET2 support for Variscite VAR-SOM-6UL module.
+ *
+ * Copyright 2019-2024 Variscite Ltd.
+ * Copyright 2026 Dimonoff
+ */
+
+/ {
+	rmii_ref_clk: rmii-ref-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+		clock-output-names = "rmii-ref";
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio_enet2: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+			clocks = <&rmii_ref_clk>;
+			clock-names = "rmii-ref";
+			reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <100000>;
+			micrel,led-mode = <0>;
+			micrel,rmii-reference-clock-select-25-mhz;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_enet2: enet2grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
+		>;
+	};
+
+	pinctrl_enet2_gpio: enet2-gpiogrp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0 /* fec2 reset */
+		>;
+	};
+
+	pinctrl_enet2_mdio: enet2-mdiogrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+		>;
+	};
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
index 7c0e313603630..89b6032203a28 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
@@ -11,6 +11,7 @@
 #include "imx6ull-var-som.dtsi"
 #include "imx6ul-var-som-concerto-common.dtsi"
 #include "imx6ul-var-som-wifi.dtsi"
+#include "imx6ul-var-som-enet2.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
index ebf88c3e1addc..f9bc6a9a5c1be 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
@@ -11,6 +11,7 @@
 #include "imx6ull-var-som.dtsi"
 #include "imx6ul-var-som-concerto-common.dtsi"
 #include "imx6ul-var-som-sd.dtsi"
+#include "imx6ul-var-som-enet2.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
-- 
2.47.3

[PATCH 11/14] ARM: dts: imx6ul-var-som: add support for EC configuration option (ENET1)

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

ENET1 is currently disabled and not supported/working on the concerto EVK.

Add support for this optional configuration in a separate DTSI include
file, so that it can be selectively enabled/disabled.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
In order for this to work, imx6ul-var-som-enet2.dtsi must be included
first, and thus enabled, even if not used. Maybe there is a better way
to support both independantly, but I'm not sure how.
---
 .../dts/nxp/imx/imx6ul-var-som-common.dtsi    | 50 -------------------
 .../imx/imx6ul-var-som-concerto-common.dtsi   |  4 --
 .../nxp/imx/imx6ul-var-som-concerto-full.dts  |  1 +
 .../dts/nxp/imx/imx6ul-var-som-enet1.dtsi     | 44 ++++++++++++++++
 .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi     | 11 ++++
 arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi |  6 +++
 .../nxp/imx/imx6ull-var-som-concerto-full.dts |  1 +
 .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi |  6 +++
 8 files changed, 69 insertions(+), 54 deletions(-)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
index af9b92f7709b4..70d19eccddb4c 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
@@ -44,57 +44,7 @@ &clks {
 	assigned-clock-rates = <786432000>;
 };
 
-&fec1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy0>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy0: ethernet-phy@1 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <1>;
-			clocks = <&rmii_ref_clk>;
-			clock-names = "rmii-ref";
-			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <100000>;
-			micrel,led-mode = <1>;
-			micrel,rmii-reference-clock-select-25-mhz;
-		};
-	};
-};
-
 &iomuxc {
-	pinctrl_enet1: enet1grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
-			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
-			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
-			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
-			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
-			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
-			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
-			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
-		>;
-	};
-
-	pinctrl_enet1_gpio: enet1-gpiogrp {
-		fsl,pins = <
-			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0 /* fec1 reset */
-		>;
-	};
-
-	pinctrl_enet1_mdio: enet1-mdiogrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
-			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
-		>;
-	};
-
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
index 53cf801f39fcd..107b1d0fe7827 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
@@ -52,10 +52,6 @@ &can1 {
 	status = "okay";
 };
 
-&fec1 {
-	status = "disabled";
-};
-
 &i2c1 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
index 3905171b47b32..b5e6a3306e1cd 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
@@ -12,6 +12,7 @@
 #include "imx6ul-var-som-concerto-common.dtsi"
 #include "imx6ul-var-som-wifi.dtsi"
 #include "imx6ul-var-som-enet2.dtsi"
+#include "imx6ul-var-som-enet1.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi
new file mode 100644
index 0000000000000..6b1e34347bec7
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Ethernet ENET1 support for Variscite VAR-SOM-6UL module with
+ * the EC configuration option ((ethernet PHY assembled on SOM).
+ *
+ * Copyright 2019-2024 Variscite Ltd.
+ * Copyright 2026 Dimonoff
+ */
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+		>;
+	};
+};
+
+&mdio_enet2 {
+	ethphy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+		clocks = <&rmii_ref_clk>;
+		clock-names = "rmii-ref";
+		reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <100000>;
+		micrel,led-mode = <1>;
+		micrel,rmii-reference-clock-select-25-mhz;
+	};
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
index 334ed3bbe02ce..b29fcdc079e37 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
@@ -26,6 +26,17 @@ mdio_enet2: mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		ethphy0: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			clocks = <&rmii_ref_clk>;
+			clock-names = "rmii-ref";
+			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <100000>;
+			micrel,led-mode = <1>;
+			micrel,rmii-reference-clock-select-25-mhz;
+		};
+
 		ethphy1: ethernet-phy@3 {
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <3>;
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
index b4e6a9316dd81..feea24c0e0683 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
@@ -29,4 +29,10 @@ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0	/* WL_PWR (WIFI_PWR 5G) */
 			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x1b0b0	/* WL_REG_ON (WIFI_EN) */
 		>;
 	};
+
+	pinctrl_enet1_gpio: enet1-gpiogrp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0 /* fec1 reset */
+		>;
+	};
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
index 89b6032203a28..86f558c76fb3e 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
@@ -12,6 +12,7 @@
 #include "imx6ul-var-som-concerto-common.dtsi"
 #include "imx6ul-var-som-wifi.dtsi"
 #include "imx6ul-var-som-enet2.dtsi"
+#include "imx6ul-var-som-enet1.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
index 3067ff6a1bc74..f120b1dca75ce 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
@@ -27,4 +27,10 @@ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0	/* WL_PWR (WIFI_PWR 5G) */
 			MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x1b0b0	/* WL_REG_ON (WIFI_EN) */
 		>;
 	};
+
+	pinctrl_enet1_gpio: enet1-gpiogrp {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0 /* fec1 reset */
+		>;
+	};
 };
-- 
2.47.3

[PATCH 12/14] ARM: dts: imx6ul-var-som: factor out audio support

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Not all boards use the audio codec, so factor out this functionality to a
separate DTSI include file.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 .../dts/nxp/imx/imx6ul-var-som-audio.dtsi     | 30 +++++++++++++++++++
 .../dts/nxp/imx/imx6ul-var-som-common.dtsi    | 21 -------------
 .../nxp/imx/imx6ul-var-som-concerto-full.dts  |  1 +
 .../dts/nxp/imx/imx6ul-var-som-concerto.dts   |  1 +
 .../nxp/imx/imx6ull-var-som-concerto-full.dts |  1 +
 .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |  1 +
 6 files changed, 34 insertions(+), 21 deletions(-)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi
new file mode 100644
index 0000000000000..3c480bc7a6ad8
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Audio support for Variscite VAR-SOM-6UL module.
+ *
+ * Copyright 2019-2024 Variscite Ltd.
+ * Copyright 2026 Dimonoff
+ */
+
+&iomuxc {
+	pinctrl_sai2: sai2grp {
+		fsl,pins = <
+			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
+			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
+			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
+			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
+			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
+		>;
+	};
+};
+
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+			  <&clks IMX6UL_CLK_SAI2>;
+	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <0>, <12288000>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
index 70d19eccddb4c..5600eeaa5854d 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
@@ -52,16 +52,6 @@ MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
 		>;
 	};
 
-	pinctrl_sai2: sai2grp {
-		fsl,pins = <
-			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
-			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
-			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
-			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
-			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
-		>;
-	};
-
 	pinctrl_tsc: tscgrp {
 		fsl,pins = <
 			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
@@ -163,17 +153,6 @@ &pxp {
 	status = "okay";
 };
 
-&sai2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_sai2>;
-	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
-			  <&clks IMX6UL_CLK_SAI2>;
-	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
-	assigned-clock-rates = <0>, <12288000>;
-	fsl,sai-mclk-direction-output;
-	status = "okay";
-};
-
 &snvs_poweroff {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
index b5e6a3306e1cd..64a3cbd8b7c38 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
@@ -13,6 +13,7 @@
 #include "imx6ul-var-som-wifi.dtsi"
 #include "imx6ul-var-som-enet2.dtsi"
 #include "imx6ul-var-som-enet1.dtsi"
+#include "imx6ul-var-som-audio.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
index d0adcd0e80833..f014ee66e18cb 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
@@ -13,6 +13,7 @@
 #include "imx6ul-var-som-concerto-common.dtsi"
 #include "imx6ul-var-som-sd.dtsi"
 #include "imx6ul-var-som-enet2.dtsi"
+#include "imx6ul-var-som-audio.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
index 86f558c76fb3e..2e1f75d5f25a6 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
@@ -13,6 +13,7 @@
 #include "imx6ul-var-som-wifi.dtsi"
 #include "imx6ul-var-som-enet2.dtsi"
 #include "imx6ul-var-som-enet1.dtsi"
+#include "imx6ul-var-som-audio.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
index f9bc6a9a5c1be..0d0613e3a34f2 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
@@ -12,6 +12,7 @@
 #include "imx6ul-var-som-concerto-common.dtsi"
 #include "imx6ul-var-som-sd.dtsi"
 #include "imx6ul-var-som-enet2.dtsi"
+#include "imx6ul-var-som-audio.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
-- 
2.47.3

[PATCH 13/14] dt-bindings: display/lvds-codec: add ti,sn65lvds93

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Add compatible string for TI SN65LVDS93. Similar to
SN65LVDS83 but with an industrial temperature range.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml
index 4f52e35d02537..f2cb74b86cc05 100644
--- a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml
@@ -37,6 +37,7 @@ properties:
               - ti,ds90c185   # For the TI DS90C185 FPD-Link Serializer
               - ti,ds90c187   # For the TI DS90C187 FPD-Link Serializer
               - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter
+              - ti,sn75lvds93 # For the TI SN75LVDS93 FlatLink transmitter
           - const: lvds-encoder # Generic LVDS encoder compatible fallback
       - items:
           - enum:
-- 
2.47.3

[PATCH 14/14] ARM: dts: imx6ul-var-som: add support for LVDS display panel

[Hugo Villeneuve]

From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Add support for the LD configuration option (LVDS encoder assembled on SOM)
so that the LVDS display panel on the concerto EVK board now works
properly.

Not all VAR-SOM-6UL SOMs have the LD configuration optionso factor out this
functionality to a separate DTSI file.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 .../imx/imx6ul-var-som-concerto-common.dtsi   |  35 ++++--
 .../nxp/imx/imx6ul-var-som-concerto-full.dts  |   1 +
 .../dts/nxp/imx/imx6ul-var-som-concerto.dts   |   1 +
 .../nxp/imx/imx6ul-var-som-lvds-panel.dtsi    | 112 ++++++++++++++++++
 .../nxp/imx/imx6ull-var-som-concerto-full.dts |   1 +
 .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |   1 +
 6 files changed, 139 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
index 107b1d0fe7827..658cec2f4d026 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
@@ -44,6 +44,29 @@ led-0 {
 			linux,default-trigger = "heartbeat";
 		};
 	};
+
+	lvds_panel: lvds-panel {
+		compatible = "sgd,gktw70sdae4se", "panel-lvds";
+		data-mapping = "jeida-18";
+		width-mm = <153>;
+		height-mm = <86>;
+
+		panel-timing {
+			clock-frequency = <35000000>;
+			hactive = <800>;
+			vactive = <480>;
+			hback-porch = <40>;
+			hfront-porch = <40>;
+			vback-porch = <29>;
+			vfront-porch = <13>;
+			hsync-len = <48>;
+			vsync-len = <3>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+		};
+	};
 };
 
 &can1 {
@@ -98,12 +121,6 @@ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
 		>;
 	};
 
-	pinctrl_pwm4: pwm4grp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO05__PWM4_OUT		0x110b0
-		>;
-	};
-
 	pinctrl_rtc: rtcgrp {
 		fsl,pins = <
 			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x1b0b0 /* RTC alarm IRQ */
@@ -139,12 +156,6 @@ MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x78b0
 	};
 };
 
-&pwm4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm4>;
-	status = "okay";
-};
-
 &snvs_pwrkey {
 	status = "disabled";
 };
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
index 64a3cbd8b7c38..725f34d6b7ee9 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
@@ -14,6 +14,7 @@
 #include "imx6ul-var-som-enet2.dtsi"
 #include "imx6ul-var-som-enet1.dtsi"
 #include "imx6ul-var-som-audio.dtsi"
+#include "imx6ul-var-som-lvds-panel.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
index f014ee66e18cb..e9e4b6882bca8 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
@@ -14,6 +14,7 @@
 #include "imx6ul-var-som-sd.dtsi"
 #include "imx6ul-var-som-enet2.dtsi"
 #include "imx6ul-var-som-audio.dtsi"
+#include "imx6ul-var-som-lvds-panel.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi
new file mode 100644
index 0000000000000..996b37d35d6e0
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * LVDS panel support for Variscite VAR-SOM-6UL module.
+ *
+ * Copyright 2019-2024 Variscite Ltd.
+ * Copyright 2026 Dimonoff
+ */
+
+/ {
+	lcd_backlight: lcd-backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm4 0 2000000 0>;
+		pwm-names = "LCD_BKLT_PWM";
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "okay";
+	};
+
+	lvds_encoder: lvds-encoder {
+		compatible = "ti,sn75lvds93", "lvds-encoder";
+		power-supply = <&reg_3p3v>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				lvds_enc_in: endpoint {
+					remote-endpoint = <&lcdif_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				lvds_enc_out: endpoint {
+					remote-endpoint = <&lvds_panel_in>;
+				};
+			};
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x79
+			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x79
+		>;
+	};
+
+	pinctrl_lcdif_dat: lcdif-dat-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x79
+			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x79
+			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x79
+			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x79
+			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x79
+			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x79
+			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x79
+			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x79
+			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x79
+			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x79
+			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x79
+			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x79
+			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x79
+			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x79
+			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x79
+			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x79
+			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x79
+			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x79
+		>;
+	};
+
+	pinctrl_pwm4: pwm4-grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO05__PWM4_OUT		0x110b0 /* LCD BACKLIGHT */
+		>;
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	status = "okay";
+
+	port {
+		lcdif_out: endpoint {
+			remote-endpoint = <&lvds_enc_in>;
+		};
+	};
+};
+
+&lvds_panel {
+	status = "okay";
+
+	port {
+		lvds_panel_in: endpoint {
+			remote-endpoint = <&lvds_enc_out>;
+		};
+	};
+};
+
+/* PWM LCD */
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>;
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
index 2e1f75d5f25a6..1b7c1a3383eec 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
@@ -14,6 +14,7 @@
 #include "imx6ul-var-som-enet2.dtsi"
 #include "imx6ul-var-som-enet1.dtsi"
 #include "imx6ul-var-som-audio.dtsi"
+#include "imx6ul-var-som-lvds-panel.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
index 0d0613e3a34f2..7d032e17134a7 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
@@ -13,6 +13,7 @@
 #include "imx6ul-var-som-sd.dtsi"
 #include "imx6ul-var-som-enet2.dtsi"
 #include "imx6ul-var-som-audio.dtsi"
+#include "imx6ul-var-som-lvds-panel.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
-- 
2.47.3

Re: [PATCH 07/14] ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU variants

[Frank Li]

On Mon, Mar 02, 2026 at 02:03:43PM -0500, Hugo Villeneuve wrote:
> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
>
> Export common parts to the Variscite VAR-SOM-6UL dtsi so that they can be
> reused on other boards.
>
> This will simplify adding future dedicated device tree files for each CPU
> variant.

Simplify adding ...

>
> Add i2c1 pinctrl to var-som dtsi pinmux, so that it can be reused by other
> boards.
>
> Reorder pinctrl_gpio_leds to respect alphabetical order.

this one use new patch.

>
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> ---
>  arch/arm/boot/dts/nxp/imx/Makefile            |   1 +
>  .../dts/nxp/imx/imx6ul-var-som-common.dtsi    |   7 +
>  ...ts => imx6ul-var-som-concerto-common.dtsi} |  17 +-
>  .../dts/nxp/imx/imx6ul-var-som-concerto.dts   | 312 +-----------------
>  .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |  17 +
>  5 files changed, 33 insertions(+), 321 deletions(-)
>  copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som-concerto.dts => imx6ul-var-som-concerto-common.dtsi} (95%)
>  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
>
> diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
> index de4142e8f3ce8..bc534d0fb1412 100644
> --- a/arch/arm/boot/dts/nxp/imx/Makefile
> +++ b/arch/arm/boot/dts/nxp/imx/Makefile
> @@ -376,6 +376,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
>  	imx6ull-tarragon-slavext.dtb \
>  	imx6ull-tqma6ull2-mba6ulx.dtb \
>  	imx6ull-tqma6ull2l-mba6ulx.dtb \
> +	imx6ull-var-som-concerto.dtb \

keep alphabet order

Frank
>  	imx6ull-uti260b.dtb \
>  	imx6ulz-14x14-evk.dtb \
>  	imx6ulz-bsh-smm-m2.dtb
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> index 2072e8ba4d469..22b0c4e0725a5 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> @@ -104,6 +104,13 @@ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x03029	/* WLAN Enable */
>  		>;
>  	};
>
> +	pinctrl_i2c1: i2c1grp {
> +		fsl,pins = <
> +			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> +			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> +		>;
> +	};
> +
>  	pinctrl_sai2: sai2grp {
>  		fsl,pins = <
>  			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> similarity index 95%
> copy from arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> copy to arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> index d16e75164fd18..10a23ae104359 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> @@ -1,19 +1,15 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
>   * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> - * Variscite SoM mounted on it
> + * Variscite SoM mounted on it, for all CPU variants.
>   *
>   * Copyright 2019 Variscite Ltd.
>   * Copyright 2025 Bootlin
>   */
>
> -#include "imx6ul-var-som.dtsi"
>  #include <dt-bindings/leds/common.h>
>
>  / {
> -	model = "Variscite VAR-SOM-6UL Concerto Board";
> -	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
> -
>  	chosen {
>  		stdout-path = &uart1;
>  	};
> @@ -144,22 +140,15 @@ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
>  		>;
>  	};
>
> -	pinctrl_gpio_leds: gpio-ledsgrp {
> -		fsl,pins = <
> -			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
> -		>;
> -	};
> -
>  	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
>  		fsl,pins = <
>  			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
>  		>;
>  	};
>
> -	pinctrl_i2c1: i2c1grp {
> +	pinctrl_gpio_leds: gpio-ledsgrp {
>  		fsl,pins = <
> -			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> -			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> +			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
>  		>;
>  	};
>
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> index d16e75164fd18..11b45f105b7ad 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> @@ -1,320 +1,18 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
>   * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> - * Variscite SoM mounted on it
> + * Variscite SoM mounted on it (6UL CPU variant).
>   *
>   * Copyright 2019 Variscite Ltd.
>   * Copyright 2025 Bootlin
>   */
>
> +/dts-v1/;
> +
>  #include "imx6ul-var-som.dtsi"
> -#include <dt-bindings/leds/common.h>
> +#include "imx6ul-var-som-concerto-common.dtsi"
>
>  / {
> -	model = "Variscite VAR-SOM-6UL Concerto Board";
> +	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
>  	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
> -
> -	chosen {
> -		stdout-path = &uart1;
> -	};
> -
> -	gpio-keys {
> -		compatible = "gpio-keys";
> -		pinctrl-names = "default";
> -		pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
> -
> -		key-back {
> -			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
> -			linux,code = <KEY_BACK>;
> -		};
> -
> -		key-wakeup {
> -			gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
> -			linux,code = <KEY_WAKEUP>;
> -			wakeup-source;
> -		};
> -	};
> -
> -	leds {
> -		compatible = "gpio-leds";
> -		pinctrl-names = "default";
> -		pinctrl-0 = <&pinctrl_gpio_leds>;
> -
> -		led-0 {
> -			function = LED_FUNCTION_STATUS;
> -			color = <LED_COLOR_ID_GREEN>;
> -			label = "gpled2";
> -			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
> -			linux,default-trigger = "heartbeat";
> -		};
> -	};
> -};
> -
> -&can1 {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_flexcan1>;
> -	status = "okay";
> -};
> -
> -&fec1 {
> -	status = "disabled";
> -};
> -
> -&fec2 {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
> -	phy-mode = "rmii";
> -	phy-handle = <&ethphy1>;
> -	status = "okay";
> -
> -	mdio {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
> -		ethphy1: ethernet-phy@3 {
> -			compatible = "ethernet-phy-ieee802.3-c22";
> -			reg = <3>;
> -			clocks = <&rmii_ref_clk>;
> -			clock-names = "rmii-ref";
> -			reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
> -			reset-assert-us = <100000>;
> -			micrel,led-mode = <0>;
> -			micrel,rmii-reference-clock-select-25-mhz;
> -		};
> -	};
> -};
> -
> -&i2c1 {
> -	clock-frequency = <100000>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_i2c1>;
> -	status = "okay";
> -
> -	rtc@68 {
> -		/*
> -		 * To actually use this interrupt
> -		 * connect pins J14.8 & J14.10 on the Concerto-Board.
> -		 */
> -		compatible = "dallas,ds1337";
> -		reg = <0x68>;
> -		pinctrl-names = "default";
> -		pinctrl-0 = <&pinctrl_rtc>;
> -		interrupt-parent = <&gpio1>;
> -		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
> -	};
> -};
> -
> -&iomuxc {
> -	pinctrl_enet2: enet2grp {
> -		fsl,pins = <
> -			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
> -			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
> -			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
> -			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
> -			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
> -			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
> -			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
> -			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
> -		>;
> -	};
> -
> -	pinctrl_enet2_gpio: enet2-gpiogrp {
> -		fsl,pins = <
> -			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0 /* fec2 reset */
> -		>;
> -	};
> -
> -	pinctrl_enet2_mdio: enet2-mdiogrp {
> -		fsl,pins = <
> -			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
> -			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
> -		>;
> -	};
> -
> -	pinctrl_flexcan1: flexcan1grp {
> -		fsl,pins = <
> -			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
> -			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
> -		>;
> -	};
> -
> -	pinctrl_gpio_key_back: gpio-key-backgrp {
> -		fsl,pins = <
> -			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
> -		>;
> -	};
> -
> -	pinctrl_gpio_leds: gpio-ledsgrp {
> -		fsl,pins = <
> -			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
> -		>;
> -	};
> -
> -	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
> -		fsl,pins = <
> -			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
> -		>;
> -	};
> -
> -	pinctrl_i2c1: i2c1grp {
> -		fsl,pins = <
> -			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> -			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> -		>;
> -	};
> -
> -	pinctrl_pwm4: pwm4grp {
> -		fsl,pins = <
> -			MX6UL_PAD_GPIO1_IO05__PWM4_OUT		0x110b0
> -		>;
> -	};
> -
> -	pinctrl_rtc: rtcgrp {
> -		fsl,pins = <
> -			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x1b0b0 /* RTC alarm IRQ */
> -		>;
> -	};
> -
> -	pinctrl_uart1: uart1grp {
> -		fsl,pins = <
> -			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
> -			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
> -		>;
> -	};
> -
> -	pinctrl_uart5: uart5grp {
> -		fsl,pins = <
> -			MX6UL_PAD_CSI_DATA00__UART5_DCE_TX	0x1b0b1
> -			MX6UL_PAD_CSI_DATA01__UART5_DCE_RX	0x1b0b1
> -			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
> -			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
> -		>;
> -	};
> -
> -	pinctrl_usb_otg1_id: usbotg1idgrp {
> -		fsl,pins = <
> -			MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID	0x17059
> -		>;
> -	};
> -
> -	pinctrl_usdhc1: usdhc1grp {
> -		fsl,pins = <
> -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
> -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
> -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
> -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
> -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
> -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
> -		>;
> -	};
> -
> -	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> -		fsl,pins = <
> -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
> -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
> -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
> -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
> -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
> -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
> -		>;
> -	};
> -
> -	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> -		fsl,pins = <
> -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
> -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
> -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
> -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
> -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
> -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
> -		>;
> -	};
> -
> -	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
> -		fsl,pins = <
> -			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
> -		>;
> -	};
> -
> -	pinctrl_wdog: wdoggrp {
> -		fsl,pins = <
> -			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x78b0
> -		>;
> -	};
> -};
> -
> -&pwm4 {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_pwm4>;
> -	status = "okay";
> -};
> -
> -&snvs_pwrkey {
> -	status = "disabled";
> -};
> -
> -&snvs_rtc {
> -	status = "disabled";
> -};
> -
> -&tsc {
> -	/*
> -	 * Conflics with wdog1 ext-reset-output & SD CD pins,
> -	 * so we keep it disabled by default.
> -	 */
> -	status = "disabled";
> -};
> -
> -/* Console UART */
> -&uart1 {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_uart1>;
> -	status = "okay";
> -};
> -
> -/* ttymxc4 UART */
> -&uart5 {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_uart5>;
> -	uart-has-rtscts;
> -	status = "okay";
> -};
> -
> -&usbotg1 {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_usb_otg1_id>;
> -	dr_mode = "otg";
> -	disable-over-current;
> -	srp-disable;
> -	hnp-disable;
> -	adp-disable;
> -	status = "okay";
> -};
> -
> -&usbotg2 {
> -	dr_mode = "host";
> -	disable-over-current;
> -	status = "okay";
> -};
> -
> -&usdhc1 {
> -	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> -	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> -	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> -	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> -	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> -	no-1-8-v;
> -	keep-power-in-suspend;
> -	wakeup-source;
> -	status = "okay";
> -};
> -
> -&wdog1 {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_wdog>;
> -	/*
> -	 * To actually use ext-reset-output
> -	 * connect pins J17.3 & J17.8 on the Concerto-Board
> -	 */
> -	fsl,ext-reset-output;
>  };
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> new file mode 100644
> index 0000000000000..7c601af2657d7
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> @@ -0,0 +1,17 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> + * Variscite SoM mounted on it (6ULL CPU variant).
> + *
> + * Copyright 2026 Dimonoff
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6ull-var-som.dtsi"
> +#include "imx6ul-var-som-concerto-common.dtsi"
> +
> +/ {
> +	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
> +	compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull";
> +};
> --
> 2.47.3
>

Re: [PATCH 08/14] ARM: dts: imx6ul-var-som: factor out SD card support

[Frank Li]

On Mon, Mar 02, 2026 at 02:03:44PM -0500, Hugo Villeneuve wrote:
> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
>
> Move SD support to a separate include, since it cannot be used at the

s/include/dtsi/

> same time as the Wifi/BT module.

what's relation ship between wifi/bt? you just move sd related part to a
dtsi file.

Frank
>
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> ---
>  .../dts/nxp/imx/imx6ul-var-som-common.dtsi    | 33 ++++++++++++
>  .../imx/imx6ul-var-som-concerto-common.dtsi   | 51 -------------------
>  .../dts/nxp/imx/imx6ul-var-som-concerto.dts   |  1 +
>  .../boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi   | 27 ++++++++++
>  .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |  1 +
>  5 files changed, 62 insertions(+), 51 deletions(-)
>  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi
>
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> index 22b0c4e0725a5..dd4ecff1eb786 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> @@ -139,6 +139,39 @@ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS	0x1b0b1
>  		>;
>  	};
>
> +	pinctrl_usdhc1: usdhc1grp {
> +		fsl,pins = <
> +			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
> +			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
> +			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
> +			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
> +			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
> +			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> +		fsl,pins = <
> +			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
> +			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
> +			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
> +			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
> +			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
> +			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> +		fsl,pins = <
> +			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
> +			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
> +			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
> +			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
> +			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
> +			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
> +		>;
> +	};
> +
>  	pinctrl_usdhc2: usdhc2grp {
>  		fsl,pins = <
>  			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10069
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> index 10a23ae104359..ea8d9905ce6e7 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> @@ -186,45 +186,6 @@ MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID	0x17059
>  		>;
>  	};
>
> -	pinctrl_usdhc1: usdhc1grp {
> -		fsl,pins = <
> -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
> -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
> -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
> -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
> -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
> -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
> -		>;
> -	};
> -
> -	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> -		fsl,pins = <
> -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
> -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
> -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
> -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
> -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
> -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
> -		>;
> -	};
> -
> -	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> -		fsl,pins = <
> -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
> -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
> -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
> -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
> -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
> -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
> -		>;
> -	};
> -
> -	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
> -		fsl,pins = <
> -			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
> -		>;
> -	};
> -
>  	pinctrl_wdog: wdoggrp {
>  		fsl,pins = <
>  			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x78b0
> @@ -286,18 +247,6 @@ &usbotg2 {
>  	status = "okay";
>  };
>
> -&usdhc1 {
> -	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> -	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> -	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> -	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> -	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> -	no-1-8-v;
> -	keep-power-in-suspend;
> -	wakeup-source;
> -	status = "okay";
> -};
> -
>  &wdog1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_wdog>;
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> index 11b45f105b7ad..85ebac30d7bed 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> @@ -11,6 +11,7 @@
>
>  #include "imx6ul-var-som.dtsi"
>  #include "imx6ul-var-som-concerto-common.dtsi"
> +#include "imx6ul-var-som-sd.dtsi"
>
>  / {
>  	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi
> new file mode 100644
> index 0000000000000..0e6d9b945eb4a
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Support optional SD card interface on Variscite VAR-SOM-6UL module.
> + *
> + * Copyright 2019-2024 Variscite Ltd.
> + * Copyright 2026 Dimonoff
> + */
> +
> +&iomuxc {
> +	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
> +		fsl,pins = <
> +			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
> +		>;
> +	};
> +};
> +
> +&usdhc1 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> +	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> +	no-1-8-v;
> +	keep-power-in-suspend;
> +	wakeup-source;
> +	status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> index 7c601af2657d7..ebf88c3e1addc 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> @@ -10,6 +10,7 @@
>
>  #include "imx6ull-var-som.dtsi"
>  #include "imx6ul-var-som-concerto-common.dtsi"
> +#include "imx6ul-var-som-sd.dtsi"
>
>  / {
>  	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
> --
> 2.47.3
>

Re: [PATCH 09/14] ARM: dts: imx6ul-var-som: add proper Wifi and Bluetooth support

[Frank Li]

On Mon, Mar 02, 2026 at 02:03:45PM -0500, Hugo Villeneuve wrote:
> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
>
> The existing configuration of the optional Wifi/Bluetooth module was
> copied from the original Variscite kernel tree, and requires custom
> scripts to properly configure the Wifi/Bluetooth module.
>
> Add proper support for the optional Wifi and Bluetooth configuration on
> VAR-SOM-6UL so that it works out of the box, without any custom scripts.
>
> The SD card interface cannot be used if the Wifi/BT module is in use.

ARM: dts: imx6ul-var-som: add proper Wifi and Bluetooth support

Add the optional Wifi and Bluetooth dtb on AR-SOM-6UL so that it works out
of the box.

The SD card interface cannot be used if the Wifi/BT module is in use.


>
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> ---
>  arch/arm/boot/dts/nxp/imx/Makefile            |  2 +
>  .../dts/nxp/imx/imx6ul-var-som-common.dtsi    | 18 ++---
>  .../nxp/imx/imx6ul-var-som-concerto-full.dts  | 18 +++++
>  .../boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi | 75 +++++++++++++++++++
>  arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 15 ++++
>  .../nxp/imx/imx6ull-var-som-concerto-full.dts | 18 +++++
>  .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 15 ++++
>  7 files changed, 151 insertions(+), 10 deletions(-)
>  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
>  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
>  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
>
> diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
> index bc534d0fb1412..c7f24ee63071f 100644
> --- a/arch/arm/boot/dts/nxp/imx/Makefile
> +++ b/arch/arm/boot/dts/nxp/imx/Makefile
> @@ -339,6 +339,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
>  	imx6ul-tx6ul-0011.dtb \
>  	imx6ul-tx6ul-mainboard.dtb \
>  	imx6ul-var-som-concerto.dtb \
> +	imx6ul-var-som-concerto-full.dtb \

how about imx6ul-var-som-concerto-wifi.dtb?

>  	imx6ull-14x14-evk.dtb \
>  	imx6ull-colibri-aster.dtb \
>  	imx6ull-colibri-emmc-aster.dtb \
> @@ -377,6 +378,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
>  	imx6ull-tqma6ull2-mba6ulx.dtb \
>  	imx6ull-tqma6ull2l-mba6ulx.dtb \
>  	imx6ull-var-som-concerto.dtb \
> +	imx6ull-var-som-concerto-full.dtb \
>  	imx6ull-uti260b.dtb \
>  	imx6ulz-14x14-evk.dtb \
>  	imx6ulz-bsh-smm-m2.dtb
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> index dd4ecff1eb786..af8c5d2db53d4 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> @@ -19,6 +19,14 @@ memory@80000000 {
>  		reg = <0x80000000 0x20000000>;
>  	};
>
> +	reg_3p3v: regulator-3p3v {
> +		compatible = "regulator-fixed";
> +		regulator-name = "3P3V";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-always-on;
> +	};
> +
>  	reg_gpio_dvfs: reg-gpio-dvfs {
>  		compatible = "regulator-gpio";
>  		regulator-min-microvolt = <1300000>;
> @@ -68,9 +76,6 @@ ethphy0: ethernet-phy@1 {
>  };
>
>  &iomuxc {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_hog>;
> -
>  	pinctrl_enet1: enet1grp {
>  		fsl,pins = <
>  			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
> @@ -97,13 +102,6 @@ MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
>  		>;
>  	};
>
> -	pinctrl_hog: hoggrp {
> -		fsl,pins = <
> -			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* BT Enable */
> -			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x03029	/* WLAN Enable */
> -		>;
> -	};
> -
>  	pinctrl_i2c1: i2c1grp {
>  		fsl,pins = <
>  			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
> new file mode 100644
> index 0000000000000..519250b31db24
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> + * Variscite SoM mounted on it (6UL CPU variant).
> + *
> + * Copyright 2026 Dimonoff
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6ul-var-som.dtsi"
> +#include "imx6ul-var-som-concerto-common.dtsi"
> +#include "imx6ul-var-som-wifi.dtsi"
> +
> +/ {
> +	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
> +	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
> +};
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
> new file mode 100644
> index 0000000000000..6d16ff7909dab
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Support optional Wifi/Bluetooth on Variscite VAR-SOM-6UL module.
> + *
> + * Copyright 2019-2024 Variscite Ltd.
> + * Copyright 2026 Dimonoff
> + */
> +
> +/ {
> +	reg_sd1_vmmc: regulator_sd1_vmmc {
> +		compatible = "regulator-fixed";
> +		regulator-name = "VMMC1";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +		startup-delay-us = <10000>;
> +	};
> +
> +	usdhc1_pwrseq: usdhc1-pwrseq {
> +		compatible = "mmc-pwrseq-simple";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_brcm_wifi>;
> +		reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl_32k_clk: 32kclkgrp {
> +		/*
> +		 * For TP option, an additional oscillator is assembled on the
> +		 * SOM to provide 32 kHz to the WiFi module. Without TP option,
> +		 * this pin is configured to provide the 32 KHz clock to the
> +		 * WiFi module.
> +		 */
> +		fsl,pins = <
> +			MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT	0x03029
> +		>;
> +	};
> +};
> +
> +&tsc {
> +	status = "disabled";
> +};
> +
> +/* Bluetooth UART */
> +&uart2 {
> +	bluetooth {
> +		compatible = "brcm,bcm43438-bt";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_brcm_bt>;
> +		shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
> +		vbat-supply = <&reg_3p3v>;
> +		vddio-supply = <&reg_3p3v>;
> +	};
> +};
> +
> +&usdhc1 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_32k_clk>;
> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_32k_clk>;
> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_32k_clk>;
> +	no-1-8-v;
> +	non-removable;
> +	mmc-pwrseq = <&usdhc1_pwrseq>;
> +	vmmc-supply = <&reg_sd1_vmmc>;
> +	status = "okay";
> +
> +	brcmf: wifi@1 {
> +		compatible = "brcm,bcm4329-fmac"; /* LWB option: Sterling LWB5 */
> +		reg = <1>;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
> index 35a0c0b3603fd..b4e6a9316dd81 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
> @@ -15,3 +15,18 @@ / {
>  	model = "Variscite VAR-SOM-6UL module";
>  	compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
>  };
> +
> +&iomuxc {
> +	pinctrl_brcm_bt: brcm-bt-grp {
> +		fsl,pins = <
> +			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* BT_REG_ON (BT_EN) */
> +		>;
> +	};
> +
> +	pinctrl_brcm_wifi: brcm-wifi-grp {
> +		fsl,pins = <
> +			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0	/* WL_PWR (WIFI_PWR 5G) */
> +			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x1b0b0	/* WL_REG_ON (WIFI_EN) */
> +		>;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
> new file mode 100644
> index 0000000000000..7c0e313603630
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> + * Variscite SoM mounted on it (6ULL CPU variant).
> + *
> + * Copyright 2026 Dimonoff
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6ull-var-som.dtsi"
> +#include "imx6ul-var-som-concerto-common.dtsi"
> +#include "imx6ul-var-som-wifi.dtsi"
> +
> +/ {
> +	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
> +	compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull";
> +};
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
> index ba482a97623b2..3067ff6a1bc74 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
> @@ -13,3 +13,18 @@ / {
>  	model = "Variscite VAR-SOM-6UL module";
>  	compatible = "variscite,var-som-imx6ull", "fsl,imx6ull";
>  };
> +
> +&iomuxc {
> +	pinctrl_brcm_bt: brcm-bt-grp {
> +		fsl,pins = <
> +			MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* BT_REG_ON (BT_EN) */
> +		>;
> +	};
> +
> +	pinctrl_brcm_wifi: brcm-wifi-grp {
> +		fsl,pins = <
> +			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0	/* WL_PWR (WIFI_PWR 5G) */
> +			MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x1b0b0	/* WL_REG_ON (WIFI_EN) */
> +		>;
> +	};
> +};
> --
> 2.47.3
>

Re: [PATCH 07/14] ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU variants

[Hugo Villeneuve]

Hi Frank,

On Mon, 2 Mar 2026 15:50:21 -0500
Frank Li <Frank.li@nxp.com> wrote:

> On Mon, Mar 02, 2026 at 02:03:43PM -0500, Hugo Villeneuve wrote:
> > From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> >
> > Export common parts to the Variscite VAR-SOM-6UL dtsi so that they can be
> > reused on other boards.
> >
> > This will simplify adding future dedicated device tree files for each CPU
> > variant.
> 
> Simplify adding ...
> 
> >
> > Add i2c1 pinctrl to var-som dtsi pinmux, so that it can be reused by other
> > boards.
> >
> > Reorder pinctrl_gpio_leds to respect alphabetical order.
> 
> this one use new patch.

I'm not sure what you mean by that? Do you mean to move this change to a
separate patch?


> 
> >
> > Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> > ---
> >  arch/arm/boot/dts/nxp/imx/Makefile            |   1 +
> >  .../dts/nxp/imx/imx6ul-var-som-common.dtsi    |   7 +
> >  ...ts => imx6ul-var-som-concerto-common.dtsi} |  17 +-
> >  .../dts/nxp/imx/imx6ul-var-som-concerto.dts   | 312 +-----------------
> >  .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |  17 +
> >  5 files changed, 33 insertions(+), 321 deletions(-)
> >  copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som-concerto.dts => imx6ul-var-som-concerto-common.dtsi} (95%)
> >  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> >
> > diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
> > index de4142e8f3ce8..bc534d0fb1412 100644
> > --- a/arch/arm/boot/dts/nxp/imx/Makefile
> > +++ b/arch/arm/boot/dts/nxp/imx/Makefile
> > @@ -376,6 +376,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> >  	imx6ull-tarragon-slavext.dtb \
> >  	imx6ull-tqma6ull2-mba6ulx.dtb \
> >  	imx6ull-tqma6ull2l-mba6ulx.dtb \
> > +	imx6ull-var-som-concerto.dtb \
> 
> keep alphabet order

Ok

> 
> Frank
> >  	imx6ull-uti260b.dtb \
> >  	imx6ulz-14x14-evk.dtb \
> >  	imx6ulz-bsh-smm-m2.dtb
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > index 2072e8ba4d469..22b0c4e0725a5 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > @@ -104,6 +104,13 @@ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x03029	/* WLAN Enable */
> >  		>;
> >  	};
> >
> > +	pinctrl_i2c1: i2c1grp {
> > +		fsl,pins = <
> > +			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> > +			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> > +		>;
> > +	};
> > +
> >  	pinctrl_sai2: sai2grp {
> >  		fsl,pins = <
> >  			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > similarity index 95%
> > copy from arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > copy to arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > index d16e75164fd18..10a23ae104359 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > @@ -1,19 +1,15 @@
> >  // SPDX-License-Identifier: GPL-2.0+
> >  /*
> >   * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> > - * Variscite SoM mounted on it
> > + * Variscite SoM mounted on it, for all CPU variants.
> >   *
> >   * Copyright 2019 Variscite Ltd.
> >   * Copyright 2025 Bootlin
> >   */
> >
> > -#include "imx6ul-var-som.dtsi"
> >  #include <dt-bindings/leds/common.h>
> >
> >  / {
> > -	model = "Variscite VAR-SOM-6UL Concerto Board";
> > -	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
> > -
> >  	chosen {
> >  		stdout-path = &uart1;
> >  	};
> > @@ -144,22 +140,15 @@ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
> >  		>;
> >  	};
> >
> > -	pinctrl_gpio_leds: gpio-ledsgrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
> > -		>;
> > -	};
> > -
> >  	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
> >  		fsl,pins = <
> >  			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
> >  		>;
> >  	};
> >
> > -	pinctrl_i2c1: i2c1grp {
> > +	pinctrl_gpio_leds: gpio-ledsgrp {
> >  		fsl,pins = <
> > -			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> > -			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> > +			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
> >  		>;
> >  	};
> >
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > index d16e75164fd18..11b45f105b7ad 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > @@ -1,320 +1,18 @@
> >  // SPDX-License-Identifier: GPL-2.0+
> >  /*
> >   * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> > - * Variscite SoM mounted on it
> > + * Variscite SoM mounted on it (6UL CPU variant).
> >   *
> >   * Copyright 2019 Variscite Ltd.
> >   * Copyright 2025 Bootlin
> >   */
> >
> > +/dts-v1/;
> > +
> >  #include "imx6ul-var-som.dtsi"
> > -#include <dt-bindings/leds/common.h>
> > +#include "imx6ul-var-som-concerto-common.dtsi"
> >
> >  / {
> > -	model = "Variscite VAR-SOM-6UL Concerto Board";
> > +	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
> >  	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
> > -
> > -	chosen {
> > -		stdout-path = &uart1;
> > -	};
> > -
> > -	gpio-keys {
> > -		compatible = "gpio-keys";
> > -		pinctrl-names = "default";
> > -		pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
> > -
> > -		key-back {
> > -			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
> > -			linux,code = <KEY_BACK>;
> > -		};
> > -
> > -		key-wakeup {
> > -			gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
> > -			linux,code = <KEY_WAKEUP>;
> > -			wakeup-source;
> > -		};
> > -	};
> > -
> > -	leds {
> > -		compatible = "gpio-leds";
> > -		pinctrl-names = "default";
> > -		pinctrl-0 = <&pinctrl_gpio_leds>;
> > -
> > -		led-0 {
> > -			function = LED_FUNCTION_STATUS;
> > -			color = <LED_COLOR_ID_GREEN>;
> > -			label = "gpled2";
> > -			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
> > -			linux,default-trigger = "heartbeat";
> > -		};
> > -	};
> > -};
> > -
> > -&can1 {
> > -	pinctrl-names = "default";
> > -	pinctrl-0 = <&pinctrl_flexcan1>;
> > -	status = "okay";
> > -};
> > -
> > -&fec1 {
> > -	status = "disabled";
> > -};
> > -
> > -&fec2 {
> > -	pinctrl-names = "default";
> > -	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
> > -	phy-mode = "rmii";
> > -	phy-handle = <&ethphy1>;
> > -	status = "okay";
> > -
> > -	mdio {
> > -		#address-cells = <1>;
> > -		#size-cells = <0>;
> > -
> > -		ethphy1: ethernet-phy@3 {
> > -			compatible = "ethernet-phy-ieee802.3-c22";
> > -			reg = <3>;
> > -			clocks = <&rmii_ref_clk>;
> > -			clock-names = "rmii-ref";
> > -			reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
> > -			reset-assert-us = <100000>;
> > -			micrel,led-mode = <0>;
> > -			micrel,rmii-reference-clock-select-25-mhz;
> > -		};
> > -	};
> > -};
> > -
> > -&i2c1 {
> > -	clock-frequency = <100000>;
> > -	pinctrl-names = "default";
> > -	pinctrl-0 = <&pinctrl_i2c1>;
> > -	status = "okay";
> > -
> > -	rtc@68 {
> > -		/*
> > -		 * To actually use this interrupt
> > -		 * connect pins J14.8 & J14.10 on the Concerto-Board.
> > -		 */
> > -		compatible = "dallas,ds1337";
> > -		reg = <0x68>;
> > -		pinctrl-names = "default";
> > -		pinctrl-0 = <&pinctrl_rtc>;
> > -		interrupt-parent = <&gpio1>;
> > -		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
> > -	};
> > -};
> > -
> > -&iomuxc {
> > -	pinctrl_enet2: enet2grp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
> > -			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
> > -			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
> > -			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
> > -			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
> > -			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
> > -			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
> > -			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
> > -		>;
> > -	};
> > -
> > -	pinctrl_enet2_gpio: enet2-gpiogrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0 /* fec2 reset */
> > -		>;
> > -	};
> > -
> > -	pinctrl_enet2_mdio: enet2-mdiogrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
> > -			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
> > -		>;
> > -	};
> > -
> > -	pinctrl_flexcan1: flexcan1grp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
> > -			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
> > -		>;
> > -	};
> > -
> > -	pinctrl_gpio_key_back: gpio-key-backgrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
> > -		>;
> > -	};
> > -
> > -	pinctrl_gpio_leds: gpio-ledsgrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
> > -		>;
> > -	};
> > -
> > -	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
> > -		>;
> > -	};
> > -
> > -	pinctrl_i2c1: i2c1grp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> > -			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> > -		>;
> > -	};
> > -
> > -	pinctrl_pwm4: pwm4grp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_GPIO1_IO05__PWM4_OUT		0x110b0
> > -		>;
> > -	};
> > -
> > -	pinctrl_rtc: rtcgrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x1b0b0 /* RTC alarm IRQ */
> > -		>;
> > -	};
> > -
> > -	pinctrl_uart1: uart1grp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
> > -			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
> > -		>;
> > -	};
> > -
> > -	pinctrl_uart5: uart5grp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_CSI_DATA00__UART5_DCE_TX	0x1b0b1
> > -			MX6UL_PAD_CSI_DATA01__UART5_DCE_RX	0x1b0b1
> > -			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
> > -			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
> > -		>;
> > -	};
> > -
> > -	pinctrl_usb_otg1_id: usbotg1idgrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID	0x17059
> > -		>;
> > -	};
> > -
> > -	pinctrl_usdhc1: usdhc1grp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
> > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
> > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
> > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
> > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
> > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
> > -		>;
> > -	};
> > -
> > -	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
> > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
> > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
> > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
> > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
> > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
> > -		>;
> > -	};
> > -
> > -	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
> > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
> > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
> > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
> > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
> > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
> > -		>;
> > -	};
> > -
> > -	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
> > -		>;
> > -	};
> > -
> > -	pinctrl_wdog: wdoggrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x78b0
> > -		>;
> > -	};
> > -};
> > -
> > -&pwm4 {
> > -	pinctrl-names = "default";
> > -	pinctrl-0 = <&pinctrl_pwm4>;
> > -	status = "okay";
> > -};
> > -
> > -&snvs_pwrkey {
> > -	status = "disabled";
> > -};
> > -
> > -&snvs_rtc {
> > -	status = "disabled";
> > -};
> > -
> > -&tsc {
> > -	/*
> > -	 * Conflics with wdog1 ext-reset-output & SD CD pins,
> > -	 * so we keep it disabled by default.
> > -	 */
> > -	status = "disabled";
> > -};
> > -
> > -/* Console UART */
> > -&uart1 {
> > -	pinctrl-names = "default";
> > -	pinctrl-0 = <&pinctrl_uart1>;
> > -	status = "okay";
> > -};
> > -
> > -/* ttymxc4 UART */
> > -&uart5 {
> > -	pinctrl-names = "default";
> > -	pinctrl-0 = <&pinctrl_uart5>;
> > -	uart-has-rtscts;
> > -	status = "okay";
> > -};
> > -
> > -&usbotg1 {
> > -	pinctrl-names = "default";
> > -	pinctrl-0 = <&pinctrl_usb_otg1_id>;
> > -	dr_mode = "otg";
> > -	disable-over-current;
> > -	srp-disable;
> > -	hnp-disable;
> > -	adp-disable;
> > -	status = "okay";
> > -};
> > -
> > -&usbotg2 {
> > -	dr_mode = "host";
> > -	disable-over-current;
> > -	status = "okay";
> > -};
> > -
> > -&usdhc1 {
> > -	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > -	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> > -	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> > -	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> > -	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> > -	no-1-8-v;
> > -	keep-power-in-suspend;
> > -	wakeup-source;
> > -	status = "okay";
> > -};
> > -
> > -&wdog1 {
> > -	pinctrl-names = "default";
> > -	pinctrl-0 = <&pinctrl_wdog>;
> > -	/*
> > -	 * To actually use ext-reset-output
> > -	 * connect pins J17.3 & J17.8 on the Concerto-Board
> > -	 */
> > -	fsl,ext-reset-output;
> >  };
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> > new file mode 100644
> > index 0000000000000..7c601af2657d7
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> > @@ -0,0 +1,17 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> > + * Variscite SoM mounted on it (6ULL CPU variant).
> > + *
> > + * Copyright 2026 Dimonoff
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx6ull-var-som.dtsi"
> > +#include "imx6ul-var-som-concerto-common.dtsi"
> > +
> > +/ {
> > +	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
> > +	compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull";
> > +};
> > --
> > 2.47.3
> >
> 


-- 
Hugo Villeneuve

Re: [PATCH 08/14] ARM: dts: imx6ul-var-som: factor out SD card support

[Hugo Villeneuve]

Hi Frank,

On Mon, 2 Mar 2026 15:54:43 -0500
Frank Li <Frank.li@nxp.com> wrote:

> On Mon, Mar 02, 2026 at 02:03:44PM -0500, Hugo Villeneuve wrote:
> > From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> >
> > Move SD support to a separate include, since it cannot be used at the
> 
> s/include/dtsi/

Ok. I will also change it in all the other commit messages.

 
> > same time as the Wifi/BT module.
> 
> what's relation ship between wifi/bt? you just move sd related part to a
> dtsi file.

As stated in commit message, the SD card interface cannot be used if
the Wifi/BT module is in use.

Sd card is not mandatory, for example on our board we do not have it,
so we need to have it disabled.

Hugo.



> 
> Frank
> >
> > Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> > ---
> >  .../dts/nxp/imx/imx6ul-var-som-common.dtsi    | 33 ++++++++++++
> >  .../imx/imx6ul-var-som-concerto-common.dtsi   | 51 -------------------
> >  .../dts/nxp/imx/imx6ul-var-som-concerto.dts   |  1 +
> >  .../boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi   | 27 ++++++++++
> >  .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |  1 +
> >  5 files changed, 62 insertions(+), 51 deletions(-)
> >  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi
> >
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > index 22b0c4e0725a5..dd4ecff1eb786 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > @@ -139,6 +139,39 @@ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS	0x1b0b1
> >  		>;
> >  	};
> >
> > +	pinctrl_usdhc1: usdhc1grp {
> > +		fsl,pins = <
> > +			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
> > +			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
> > +			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
> > +			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
> > +			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
> > +			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> > +		fsl,pins = <
> > +			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
> > +			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
> > +			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
> > +			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
> > +			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
> > +			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> > +		fsl,pins = <
> > +			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
> > +			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
> > +			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
> > +			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
> > +			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
> > +			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
> > +		>;
> > +	};
> > +
> >  	pinctrl_usdhc2: usdhc2grp {
> >  		fsl,pins = <
> >  			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10069
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > index 10a23ae104359..ea8d9905ce6e7 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > @@ -186,45 +186,6 @@ MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID	0x17059
> >  		>;
> >  	};
> >
> > -	pinctrl_usdhc1: usdhc1grp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
> > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
> > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
> > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
> > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
> > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
> > -		>;
> > -	};
> > -
> > -	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
> > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
> > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
> > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
> > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
> > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
> > -		>;
> > -	};
> > -
> > -	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
> > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
> > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
> > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
> > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
> > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
> > -		>;
> > -	};
> > -
> > -	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
> > -		>;
> > -	};
> > -
> >  	pinctrl_wdog: wdoggrp {
> >  		fsl,pins = <
> >  			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x78b0
> > @@ -286,18 +247,6 @@ &usbotg2 {
> >  	status = "okay";
> >  };
> >
> > -&usdhc1 {
> > -	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > -	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> > -	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> > -	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> > -	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> > -	no-1-8-v;
> > -	keep-power-in-suspend;
> > -	wakeup-source;
> > -	status = "okay";
> > -};
> > -
> >  &wdog1 {
> >  	pinctrl-names = "default";
> >  	pinctrl-0 = <&pinctrl_wdog>;
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > index 11b45f105b7ad..85ebac30d7bed 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > @@ -11,6 +11,7 @@
> >
> >  #include "imx6ul-var-som.dtsi"
> >  #include "imx6ul-var-som-concerto-common.dtsi"
> > +#include "imx6ul-var-som-sd.dtsi"
> >
> >  / {
> >  	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi
> > new file mode 100644
> > index 0000000000000..0e6d9b945eb4a
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi
> > @@ -0,0 +1,27 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Support optional SD card interface on Variscite VAR-SOM-6UL module.
> > + *
> > + * Copyright 2019-2024 Variscite Ltd.
> > + * Copyright 2026 Dimonoff
> > + */
> > +
> > +&iomuxc {
> > +	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
> > +		fsl,pins = <
> > +			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
> > +		>;
> > +	};
> > +};
> > +
> > +&usdhc1 {
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> > +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> > +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> > +	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> > +	no-1-8-v;
> > +	keep-power-in-suspend;
> > +	wakeup-source;
> > +	status = "okay";
> > +};
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> > index 7c601af2657d7..ebf88c3e1addc 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> > @@ -10,6 +10,7 @@
> >
> >  #include "imx6ull-var-som.dtsi"
> >  #include "imx6ul-var-som-concerto-common.dtsi"
> > +#include "imx6ul-var-som-sd.dtsi"
> >
> >  / {
> >  	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
> > --
> > 2.47.3
> >
> 


-- 
Hugo Villeneuve

Re: [PATCH 07/14] ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU variants

[Frank Li]

On Mon, Mar 02, 2026 at 04:07:31PM -0500, Hugo Villeneuve wrote:
> Hi Frank,
>
> On Mon, 2 Mar 2026 15:50:21 -0500
> Frank Li <Frank.li@nxp.com> wrote:
>
> > On Mon, Mar 02, 2026 at 02:03:43PM -0500, Hugo Villeneuve wrote:
> > > From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> > >
> > > Export common parts to the Variscite VAR-SOM-6UL dtsi so that they can be
> > > reused on other boards.
> > >
> > > This will simplify adding future dedicated device tree files for each CPU
> > > variant.
> >
> > Simplify adding ...
> >
> > >
> > > Add i2c1 pinctrl to var-som dtsi pinmux, so that it can be reused by other
> > > boards.
> > >
> > > Reorder pinctrl_gpio_leds to respect alphabetical order.
> >
> > this one use new patch.
>
> I'm not sure what you mean by that? Do you mean to move this change to a
> separate patch?

yes

Frank
>
>
> >
> > >
> > > Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> > > ---
> > >  arch/arm/boot/dts/nxp/imx/Makefile            |   1 +
> > >  .../dts/nxp/imx/imx6ul-var-som-common.dtsi    |   7 +
> > >  ...ts => imx6ul-var-som-concerto-common.dtsi} |  17 +-
> > >  .../dts/nxp/imx/imx6ul-var-som-concerto.dts   | 312 +-----------------
> > >  .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |  17 +
> > >  5 files changed, 33 insertions(+), 321 deletions(-)
> > >  copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som-concerto.dts => imx6ul-var-som-concerto-common.dtsi} (95%)
> > >  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> > >
> > > diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
> > > index de4142e8f3ce8..bc534d0fb1412 100644
> > > --- a/arch/arm/boot/dts/nxp/imx/Makefile
> > > +++ b/arch/arm/boot/dts/nxp/imx/Makefile
> > > @@ -376,6 +376,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> > >  	imx6ull-tarragon-slavext.dtb \
> > >  	imx6ull-tqma6ull2-mba6ulx.dtb \
> > >  	imx6ull-tqma6ull2l-mba6ulx.dtb \
> > > +	imx6ull-var-som-concerto.dtb \
> >
> > keep alphabet order
>
> Ok
>
> >
> > Frank
> > >  	imx6ull-uti260b.dtb \
> > >  	imx6ulz-14x14-evk.dtb \
> > >  	imx6ulz-bsh-smm-m2.dtb
> > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > > index 2072e8ba4d469..22b0c4e0725a5 100644
> > > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > > @@ -104,6 +104,13 @@ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x03029	/* WLAN Enable */
> > >  		>;
> > >  	};
> > >
> > > +	pinctrl_i2c1: i2c1grp {
> > > +		fsl,pins = <
> > > +			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> > > +			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> > > +		>;
> > > +	};
> > > +
> > >  	pinctrl_sai2: sai2grp {
> > >  		fsl,pins = <
> > >  			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
> > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > > similarity index 95%
> > > copy from arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > > copy to arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > > index d16e75164fd18..10a23ae104359 100644
> > > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > > @@ -1,19 +1,15 @@
> > >  // SPDX-License-Identifier: GPL-2.0+
> > >  /*
> > >   * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> > > - * Variscite SoM mounted on it
> > > + * Variscite SoM mounted on it, for all CPU variants.
> > >   *
> > >   * Copyright 2019 Variscite Ltd.
> > >   * Copyright 2025 Bootlin
> > >   */
> > >
> > > -#include "imx6ul-var-som.dtsi"
> > >  #include <dt-bindings/leds/common.h>
> > >
> > >  / {
> > > -	model = "Variscite VAR-SOM-6UL Concerto Board";
> > > -	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
> > > -
> > >  	chosen {
> > >  		stdout-path = &uart1;
> > >  	};
> > > @@ -144,22 +140,15 @@ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
> > >  		>;
> > >  	};
> > >
> > > -	pinctrl_gpio_leds: gpio-ledsgrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
> > > -		>;
> > > -	};
> > > -
> > >  	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
> > >  		fsl,pins = <
> > >  			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
> > >  		>;
> > >  	};
> > >
> > > -	pinctrl_i2c1: i2c1grp {
> > > +	pinctrl_gpio_leds: gpio-ledsgrp {
> > >  		fsl,pins = <
> > > -			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> > > -			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> > > +			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
> > >  		>;
> > >  	};
> > >
> > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > > index d16e75164fd18..11b45f105b7ad 100644
> > > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > > @@ -1,320 +1,18 @@
> > >  // SPDX-License-Identifier: GPL-2.0+
> > >  /*
> > >   * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> > > - * Variscite SoM mounted on it
> > > + * Variscite SoM mounted on it (6UL CPU variant).
> > >   *
> > >   * Copyright 2019 Variscite Ltd.
> > >   * Copyright 2025 Bootlin
> > >   */
> > >
> > > +/dts-v1/;
> > > +
> > >  #include "imx6ul-var-som.dtsi"
> > > -#include <dt-bindings/leds/common.h>
> > > +#include "imx6ul-var-som-concerto-common.dtsi"
> > >
> > >  / {
> > > -	model = "Variscite VAR-SOM-6UL Concerto Board";
> > > +	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
> > >  	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
> > > -
> > > -	chosen {
> > > -		stdout-path = &uart1;
> > > -	};
> > > -
> > > -	gpio-keys {
> > > -		compatible = "gpio-keys";
> > > -		pinctrl-names = "default";
> > > -		pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
> > > -
> > > -		key-back {
> > > -			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
> > > -			linux,code = <KEY_BACK>;
> > > -		};
> > > -
> > > -		key-wakeup {
> > > -			gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
> > > -			linux,code = <KEY_WAKEUP>;
> > > -			wakeup-source;
> > > -		};
> > > -	};
> > > -
> > > -	leds {
> > > -		compatible = "gpio-leds";
> > > -		pinctrl-names = "default";
> > > -		pinctrl-0 = <&pinctrl_gpio_leds>;
> > > -
> > > -		led-0 {
> > > -			function = LED_FUNCTION_STATUS;
> > > -			color = <LED_COLOR_ID_GREEN>;
> > > -			label = "gpled2";
> > > -			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
> > > -			linux,default-trigger = "heartbeat";
> > > -		};
> > > -	};
> > > -};
> > > -
> > > -&can1 {
> > > -	pinctrl-names = "default";
> > > -	pinctrl-0 = <&pinctrl_flexcan1>;
> > > -	status = "okay";
> > > -};
> > > -
> > > -&fec1 {
> > > -	status = "disabled";
> > > -};
> > > -
> > > -&fec2 {
> > > -	pinctrl-names = "default";
> > > -	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
> > > -	phy-mode = "rmii";
> > > -	phy-handle = <&ethphy1>;
> > > -	status = "okay";
> > > -
> > > -	mdio {
> > > -		#address-cells = <1>;
> > > -		#size-cells = <0>;
> > > -
> > > -		ethphy1: ethernet-phy@3 {
> > > -			compatible = "ethernet-phy-ieee802.3-c22";
> > > -			reg = <3>;
> > > -			clocks = <&rmii_ref_clk>;
> > > -			clock-names = "rmii-ref";
> > > -			reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
> > > -			reset-assert-us = <100000>;
> > > -			micrel,led-mode = <0>;
> > > -			micrel,rmii-reference-clock-select-25-mhz;
> > > -		};
> > > -	};
> > > -};
> > > -
> > > -&i2c1 {
> > > -	clock-frequency = <100000>;
> > > -	pinctrl-names = "default";
> > > -	pinctrl-0 = <&pinctrl_i2c1>;
> > > -	status = "okay";
> > > -
> > > -	rtc@68 {
> > > -		/*
> > > -		 * To actually use this interrupt
> > > -		 * connect pins J14.8 & J14.10 on the Concerto-Board.
> > > -		 */
> > > -		compatible = "dallas,ds1337";
> > > -		reg = <0x68>;
> > > -		pinctrl-names = "default";
> > > -		pinctrl-0 = <&pinctrl_rtc>;
> > > -		interrupt-parent = <&gpio1>;
> > > -		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
> > > -	};
> > > -};
> > > -
> > > -&iomuxc {
> > > -	pinctrl_enet2: enet2grp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
> > > -			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
> > > -			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
> > > -			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
> > > -			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
> > > -			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
> > > -			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
> > > -			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_enet2_gpio: enet2-gpiogrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0 /* fec2 reset */
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_enet2_mdio: enet2-mdiogrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
> > > -			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_flexcan1: flexcan1grp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
> > > -			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_gpio_key_back: gpio-key-backgrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_gpio_leds: gpio-ledsgrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_i2c1: i2c1grp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> > > -			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_pwm4: pwm4grp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_GPIO1_IO05__PWM4_OUT		0x110b0
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_rtc: rtcgrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x1b0b0 /* RTC alarm IRQ */
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_uart1: uart1grp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
> > > -			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_uart5: uart5grp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_CSI_DATA00__UART5_DCE_TX	0x1b0b1
> > > -			MX6UL_PAD_CSI_DATA01__UART5_DCE_RX	0x1b0b1
> > > -			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
> > > -			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_usb_otg1_id: usbotg1idgrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID	0x17059
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_usdhc1: usdhc1grp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
> > > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
> > > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
> > > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
> > > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
> > > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
> > > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
> > > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
> > > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
> > > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
> > > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
> > > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
> > > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
> > > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
> > > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
> > > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
> > > -		>;
> > > -	};
> > > -
> > > -	pinctrl_wdog: wdoggrp {
> > > -		fsl,pins = <
> > > -			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x78b0
> > > -		>;
> > > -	};
> > > -};
> > > -
> > > -&pwm4 {
> > > -	pinctrl-names = "default";
> > > -	pinctrl-0 = <&pinctrl_pwm4>;
> > > -	status = "okay";
> > > -};
> > > -
> > > -&snvs_pwrkey {
> > > -	status = "disabled";
> > > -};
> > > -
> > > -&snvs_rtc {
> > > -	status = "disabled";
> > > -};
> > > -
> > > -&tsc {
> > > -	/*
> > > -	 * Conflics with wdog1 ext-reset-output & SD CD pins,
> > > -	 * so we keep it disabled by default.
> > > -	 */
> > > -	status = "disabled";
> > > -};
> > > -
> > > -/* Console UART */
> > > -&uart1 {
> > > -	pinctrl-names = "default";
> > > -	pinctrl-0 = <&pinctrl_uart1>;
> > > -	status = "okay";
> > > -};
> > > -
> > > -/* ttymxc4 UART */
> > > -&uart5 {
> > > -	pinctrl-names = "default";
> > > -	pinctrl-0 = <&pinctrl_uart5>;
> > > -	uart-has-rtscts;
> > > -	status = "okay";
> > > -};
> > > -
> > > -&usbotg1 {
> > > -	pinctrl-names = "default";
> > > -	pinctrl-0 = <&pinctrl_usb_otg1_id>;
> > > -	dr_mode = "otg";
> > > -	disable-over-current;
> > > -	srp-disable;
> > > -	hnp-disable;
> > > -	adp-disable;
> > > -	status = "okay";
> > > -};
> > > -
> > > -&usbotg2 {
> > > -	dr_mode = "host";
> > > -	disable-over-current;
> > > -	status = "okay";
> > > -};
> > > -
> > > -&usdhc1 {
> > > -	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > > -	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> > > -	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> > > -	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> > > -	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> > > -	no-1-8-v;
> > > -	keep-power-in-suspend;
> > > -	wakeup-source;
> > > -	status = "okay";
> > > -};
> > > -
> > > -&wdog1 {
> > > -	pinctrl-names = "default";
> > > -	pinctrl-0 = <&pinctrl_wdog>;
> > > -	/*
> > > -	 * To actually use ext-reset-output
> > > -	 * connect pins J17.3 & J17.8 on the Concerto-Board
> > > -	 */
> > > -	fsl,ext-reset-output;
> > >  };
> > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> > > new file mode 100644
> > > index 0000000000000..7c601af2657d7
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> > > @@ -0,0 +1,17 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> > > + * Variscite SoM mounted on it (6ULL CPU variant).
> > > + *
> > > + * Copyright 2026 Dimonoff
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "imx6ull-var-som.dtsi"
> > > +#include "imx6ul-var-som-concerto-common.dtsi"
> > > +
> > > +/ {
> > > +	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
> > > +	compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull";
> > > +};
> > > --
> > > 2.47.3
> > >
> >
>
>
> --
> Hugo Villeneuve

Re: [PATCH 07/14] ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU variants

[Hugo Villeneuve]

Hi Frank,

On Mon, 2 Mar 2026 16:28:17 -0500
Frank Li <Frank.li@nxp.com> wrote:

> On Mon, Mar 02, 2026 at 04:07:31PM -0500, Hugo Villeneuve wrote:
> > Hi Frank,
> >
> > On Mon, 2 Mar 2026 15:50:21 -0500
> > Frank Li <Frank.li@nxp.com> wrote:
> >
> > > On Mon, Mar 02, 2026 at 02:03:43PM -0500, Hugo Villeneuve wrote:
> > > > From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> > > >
> > > > Export common parts to the Variscite VAR-SOM-6UL dtsi so that they can be
> > > > reused on other boards.
> > > >
> > > > This will simplify adding future dedicated device tree files for each CPU
> > > > variant.
> > >
> > > Simplify adding ...
> > >
> > > >
> > > > Add i2c1 pinctrl to var-som dtsi pinmux, so that it can be reused by other
> > > > boards.
> > > >
> > > > Reorder pinctrl_gpio_leds to respect alphabetical order.
> > >
> > > this one use new patch.
> >
> > I'm not sure what you mean by that? Do you mean to move this change to a
> > separate patch?
> 
> yes

Ok, will do for V2.

Thnak you,
Hugo.


> 
> Frank
> >
> >
> > >
> > > >
> > > > Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> > > > ---
> > > >  arch/arm/boot/dts/nxp/imx/Makefile            |   1 +
> > > >  .../dts/nxp/imx/imx6ul-var-som-common.dtsi    |   7 +
> > > >  ...ts => imx6ul-var-som-concerto-common.dtsi} |  17 +-
> > > >  .../dts/nxp/imx/imx6ul-var-som-concerto.dts   | 312 +-----------------
> > > >  .../dts/nxp/imx/imx6ull-var-som-concerto.dts  |  17 +
> > > >  5 files changed, 33 insertions(+), 321 deletions(-)
> > > >  copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som-concerto.dts => imx6ul-var-som-concerto-common.dtsi} (95%)
> > > >  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> > > >
> > > > diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
> > > > index de4142e8f3ce8..bc534d0fb1412 100644
> > > > --- a/arch/arm/boot/dts/nxp/imx/Makefile
> > > > +++ b/arch/arm/boot/dts/nxp/imx/Makefile
> > > > @@ -376,6 +376,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> > > >  	imx6ull-tarragon-slavext.dtb \
> > > >  	imx6ull-tqma6ull2-mba6ulx.dtb \
> > > >  	imx6ull-tqma6ull2l-mba6ulx.dtb \
> > > > +	imx6ull-var-som-concerto.dtb \
> > >
> > > keep alphabet order
> >
> > Ok
> >
> > >
> > > Frank
> > > >  	imx6ull-uti260b.dtb \
> > > >  	imx6ulz-14x14-evk.dtb \
> > > >  	imx6ulz-bsh-smm-m2.dtb
> > > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > > > index 2072e8ba4d469..22b0c4e0725a5 100644
> > > > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > > > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > > > @@ -104,6 +104,13 @@ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x03029	/* WLAN Enable */
> > > >  		>;
> > > >  	};
> > > >
> > > > +	pinctrl_i2c1: i2c1grp {
> > > > +		fsl,pins = <
> > > > +			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> > > > +			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> > > > +		>;
> > > > +	};
> > > > +
> > > >  	pinctrl_sai2: sai2grp {
> > > >  		fsl,pins = <
> > > >  			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
> > > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > > > similarity index 95%
> > > > copy from arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > > > copy to arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > > > index d16e75164fd18..10a23ae104359 100644
> > > > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > > > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
> > > > @@ -1,19 +1,15 @@
> > > >  // SPDX-License-Identifier: GPL-2.0+
> > > >  /*
> > > >   * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> > > > - * Variscite SoM mounted on it
> > > > + * Variscite SoM mounted on it, for all CPU variants.
> > > >   *
> > > >   * Copyright 2019 Variscite Ltd.
> > > >   * Copyright 2025 Bootlin
> > > >   */
> > > >
> > > > -#include "imx6ul-var-som.dtsi"
> > > >  #include <dt-bindings/leds/common.h>
> > > >
> > > >  / {
> > > > -	model = "Variscite VAR-SOM-6UL Concerto Board";
> > > > -	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
> > > > -
> > > >  	chosen {
> > > >  		stdout-path = &uart1;
> > > >  	};
> > > > @@ -144,22 +140,15 @@ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
> > > >  		>;
> > > >  	};
> > > >
> > > > -	pinctrl_gpio_leds: gpio-ledsgrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
> > > > -		>;
> > > > -	};
> > > > -
> > > >  	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
> > > >  		fsl,pins = <
> > > >  			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
> > > >  		>;
> > > >  	};
> > > >
> > > > -	pinctrl_i2c1: i2c1grp {
> > > > +	pinctrl_gpio_leds: gpio-ledsgrp {
> > > >  		fsl,pins = <
> > > > -			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> > > > -			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> > > > +			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
> > > >  		>;
> > > >  	};
> > > >
> > > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > > > index d16e75164fd18..11b45f105b7ad 100644
> > > > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > > > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> > > > @@ -1,320 +1,18 @@
> > > >  // SPDX-License-Identifier: GPL-2.0+
> > > >  /*
> > > >   * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> > > > - * Variscite SoM mounted on it
> > > > + * Variscite SoM mounted on it (6UL CPU variant).
> > > >   *
> > > >   * Copyright 2019 Variscite Ltd.
> > > >   * Copyright 2025 Bootlin
> > > >   */
> > > >
> > > > +/dts-v1/;
> > > > +
> > > >  #include "imx6ul-var-som.dtsi"
> > > > -#include <dt-bindings/leds/common.h>
> > > > +#include "imx6ul-var-som-concerto-common.dtsi"
> > > >
> > > >  / {
> > > > -	model = "Variscite VAR-SOM-6UL Concerto Board";
> > > > +	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
> > > >  	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
> > > > -
> > > > -	chosen {
> > > > -		stdout-path = &uart1;
> > > > -	};
> > > > -
> > > > -	gpio-keys {
> > > > -		compatible = "gpio-keys";
> > > > -		pinctrl-names = "default";
> > > > -		pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
> > > > -
> > > > -		key-back {
> > > > -			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
> > > > -			linux,code = <KEY_BACK>;
> > > > -		};
> > > > -
> > > > -		key-wakeup {
> > > > -			gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
> > > > -			linux,code = <KEY_WAKEUP>;
> > > > -			wakeup-source;
> > > > -		};
> > > > -	};
> > > > -
> > > > -	leds {
> > > > -		compatible = "gpio-leds";
> > > > -		pinctrl-names = "default";
> > > > -		pinctrl-0 = <&pinctrl_gpio_leds>;
> > > > -
> > > > -		led-0 {
> > > > -			function = LED_FUNCTION_STATUS;
> > > > -			color = <LED_COLOR_ID_GREEN>;
> > > > -			label = "gpled2";
> > > > -			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
> > > > -			linux,default-trigger = "heartbeat";
> > > > -		};
> > > > -	};
> > > > -};
> > > > -
> > > > -&can1 {
> > > > -	pinctrl-names = "default";
> > > > -	pinctrl-0 = <&pinctrl_flexcan1>;
> > > > -	status = "okay";
> > > > -};
> > > > -
> > > > -&fec1 {
> > > > -	status = "disabled";
> > > > -};
> > > > -
> > > > -&fec2 {
> > > > -	pinctrl-names = "default";
> > > > -	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
> > > > -	phy-mode = "rmii";
> > > > -	phy-handle = <&ethphy1>;
> > > > -	status = "okay";
> > > > -
> > > > -	mdio {
> > > > -		#address-cells = <1>;
> > > > -		#size-cells = <0>;
> > > > -
> > > > -		ethphy1: ethernet-phy@3 {
> > > > -			compatible = "ethernet-phy-ieee802.3-c22";
> > > > -			reg = <3>;
> > > > -			clocks = <&rmii_ref_clk>;
> > > > -			clock-names = "rmii-ref";
> > > > -			reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
> > > > -			reset-assert-us = <100000>;
> > > > -			micrel,led-mode = <0>;
> > > > -			micrel,rmii-reference-clock-select-25-mhz;
> > > > -		};
> > > > -	};
> > > > -};
> > > > -
> > > > -&i2c1 {
> > > > -	clock-frequency = <100000>;
> > > > -	pinctrl-names = "default";
> > > > -	pinctrl-0 = <&pinctrl_i2c1>;
> > > > -	status = "okay";
> > > > -
> > > > -	rtc@68 {
> > > > -		/*
> > > > -		 * To actually use this interrupt
> > > > -		 * connect pins J14.8 & J14.10 on the Concerto-Board.
> > > > -		 */
> > > > -		compatible = "dallas,ds1337";
> > > > -		reg = <0x68>;
> > > > -		pinctrl-names = "default";
> > > > -		pinctrl-0 = <&pinctrl_rtc>;
> > > > -		interrupt-parent = <&gpio1>;
> > > > -		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
> > > > -	};
> > > > -};
> > > > -
> > > > -&iomuxc {
> > > > -	pinctrl_enet2: enet2grp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
> > > > -			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
> > > > -			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
> > > > -			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
> > > > -			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
> > > > -			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
> > > > -			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
> > > > -			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_enet2_gpio: enet2-gpiogrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0 /* fec2 reset */
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_enet2_mdio: enet2-mdiogrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
> > > > -			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_flexcan1: flexcan1grp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
> > > > -			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_gpio_key_back: gpio-key-backgrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_gpio_leds: gpio-ledsgrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_i2c1: i2c1grp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> > > > -			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_pwm4: pwm4grp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_GPIO1_IO05__PWM4_OUT		0x110b0
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_rtc: rtcgrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x1b0b0 /* RTC alarm IRQ */
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_uart1: uart1grp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
> > > > -			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_uart5: uart5grp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_CSI_DATA00__UART5_DCE_TX	0x1b0b1
> > > > -			MX6UL_PAD_CSI_DATA01__UART5_DCE_RX	0x1b0b1
> > > > -			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
> > > > -			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_usb_otg1_id: usbotg1idgrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID	0x17059
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_usdhc1: usdhc1grp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
> > > > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
> > > > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
> > > > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
> > > > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
> > > > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
> > > > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
> > > > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
> > > > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
> > > > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
> > > > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
> > > > -			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
> > > > -			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
> > > > -			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
> > > > -			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
> > > > -			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
> > > > -		>;
> > > > -	};
> > > > -
> > > > -	pinctrl_wdog: wdoggrp {
> > > > -		fsl,pins = <
> > > > -			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x78b0
> > > > -		>;
> > > > -	};
> > > > -};
> > > > -
> > > > -&pwm4 {
> > > > -	pinctrl-names = "default";
> > > > -	pinctrl-0 = <&pinctrl_pwm4>;
> > > > -	status = "okay";
> > > > -};
> > > > -
> > > > -&snvs_pwrkey {
> > > > -	status = "disabled";
> > > > -};
> > > > -
> > > > -&snvs_rtc {
> > > > -	status = "disabled";
> > > > -};
> > > > -
> > > > -&tsc {
> > > > -	/*
> > > > -	 * Conflics with wdog1 ext-reset-output & SD CD pins,
> > > > -	 * so we keep it disabled by default.
> > > > -	 */
> > > > -	status = "disabled";
> > > > -};
> > > > -
> > > > -/* Console UART */
> > > > -&uart1 {
> > > > -	pinctrl-names = "default";
> > > > -	pinctrl-0 = <&pinctrl_uart1>;
> > > > -	status = "okay";
> > > > -};
> > > > -
> > > > -/* ttymxc4 UART */
> > > > -&uart5 {
> > > > -	pinctrl-names = "default";
> > > > -	pinctrl-0 = <&pinctrl_uart5>;
> > > > -	uart-has-rtscts;
> > > > -	status = "okay";
> > > > -};
> > > > -
> > > > -&usbotg1 {
> > > > -	pinctrl-names = "default";
> > > > -	pinctrl-0 = <&pinctrl_usb_otg1_id>;
> > > > -	dr_mode = "otg";
> > > > -	disable-over-current;
> > > > -	srp-disable;
> > > > -	hnp-disable;
> > > > -	adp-disable;
> > > > -	status = "okay";
> > > > -};
> > > > -
> > > > -&usbotg2 {
> > > > -	dr_mode = "host";
> > > > -	disable-over-current;
> > > > -	status = "okay";
> > > > -};
> > > > -
> > > > -&usdhc1 {
> > > > -	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > > > -	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> > > > -	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> > > > -	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> > > > -	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> > > > -	no-1-8-v;
> > > > -	keep-power-in-suspend;
> > > > -	wakeup-source;
> > > > -	status = "okay";
> > > > -};
> > > > -
> > > > -&wdog1 {
> > > > -	pinctrl-names = "default";
> > > > -	pinctrl-0 = <&pinctrl_wdog>;
> > > > -	/*
> > > > -	 * To actually use ext-reset-output
> > > > -	 * connect pins J17.3 & J17.8 on the Concerto-Board
> > > > -	 */
> > > > -	fsl,ext-reset-output;
> > > >  };
> > > > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> > > > new file mode 100644
> > > > index 0000000000000..7c601af2657d7
> > > > --- /dev/null
> > > > +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
> > > > @@ -0,0 +1,17 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> > > > + * Variscite SoM mounted on it (6ULL CPU variant).
> > > > + *
> > > > + * Copyright 2026 Dimonoff
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +
> > > > +#include "imx6ull-var-som.dtsi"
> > > > +#include "imx6ul-var-som-concerto-common.dtsi"
> > > > +
> > > > +/ {
> > > > +	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
> > > > +	compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull";
> > > > +};
> > > > --
> > > > 2.47.3
> > > >
> > >
> >
> >
> > --
> > Hugo Villeneuve
> 


-- 
Hugo Villeneuve

Re: [PATCH 09/14] ARM: dts: imx6ul-var-som: add proper Wifi and Bluetooth support

[Hugo Villeneuve]

On Mon, 2 Mar 2026 15:59:43 -0500
Frank Li <Frank.li@nxp.com> wrote:

> On Mon, Mar 02, 2026 at 02:03:45PM -0500, Hugo Villeneuve wrote:
> > From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> >
> > The existing configuration of the optional Wifi/Bluetooth module was
> > copied from the original Variscite kernel tree, and requires custom
> > scripts to properly configure the Wifi/Bluetooth module.
> >
> > Add proper support for the optional Wifi and Bluetooth configuration on
> > VAR-SOM-6UL so that it works out of the box, without any custom scripts.
> >
> > The SD card interface cannot be used if the Wifi/BT module is in use.
> 
> ARM: dts: imx6ul-var-som: add proper Wifi and Bluetooth support

This looks identical to the initial commit message?

> Add the optional Wifi and Bluetooth dtb on AR-SOM-6UL so that it works out
> of the box.

See comments below about name of dtb.


> The SD card interface cannot be used if the Wifi/BT module is in use.
> 
> 
> >
> > Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> > ---
> >  arch/arm/boot/dts/nxp/imx/Makefile            |  2 +
> >  .../dts/nxp/imx/imx6ul-var-som-common.dtsi    | 18 ++---
> >  .../nxp/imx/imx6ul-var-som-concerto-full.dts  | 18 +++++
> >  .../boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi | 75 +++++++++++++++++++
> >  arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 15 ++++
> >  .../nxp/imx/imx6ull-var-som-concerto-full.dts | 18 +++++
> >  .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 15 ++++
> >  7 files changed, 151 insertions(+), 10 deletions(-)
> >  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
> >  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
> >  create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
> >
> > diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
> > index bc534d0fb1412..c7f24ee63071f 100644
> > --- a/arch/arm/boot/dts/nxp/imx/Makefile
> > +++ b/arch/arm/boot/dts/nxp/imx/Makefile
> > @@ -339,6 +339,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> >  	imx6ul-tx6ul-0011.dtb \
> >  	imx6ul-tx6ul-mainboard.dtb \
> >  	imx6ul-var-som-concerto.dtb \
> > +	imx6ul-var-som-concerto-full.dtb \
> 
> how about imx6ul-var-som-concerto-wifi.dtb?

There is an exponential number of possible configurations (sd + wifi,
eemc + wifi, eemc + eth and no wifi, etc). To simplify, I am simply
adding a full DTB which will support all options on the EVK.

Hugo.


> >  	imx6ull-14x14-evk.dtb \
> >  	imx6ull-colibri-aster.dtb \
> >  	imx6ull-colibri-emmc-aster.dtb \
> > @@ -377,6 +378,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> >  	imx6ull-tqma6ull2-mba6ulx.dtb \
> >  	imx6ull-tqma6ull2l-mba6ulx.dtb \
> >  	imx6ull-var-som-concerto.dtb \
> > +	imx6ull-var-som-concerto-full.dtb \
> >  	imx6ull-uti260b.dtb \
> >  	imx6ulz-14x14-evk.dtb \
> >  	imx6ulz-bsh-smm-m2.dtb
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > index dd4ecff1eb786..af8c5d2db53d4 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
> > @@ -19,6 +19,14 @@ memory@80000000 {
> >  		reg = <0x80000000 0x20000000>;
> >  	};
> >
> > +	reg_3p3v: regulator-3p3v {
> > +		compatible = "regulator-fixed";
> > +		regulator-name = "3P3V";
> > +		regulator-min-microvolt = <3300000>;
> > +		regulator-max-microvolt = <3300000>;
> > +		regulator-always-on;
> > +	};
> > +
> >  	reg_gpio_dvfs: reg-gpio-dvfs {
> >  		compatible = "regulator-gpio";
> >  		regulator-min-microvolt = <1300000>;
> > @@ -68,9 +76,6 @@ ethphy0: ethernet-phy@1 {
> >  };
> >
> >  &iomuxc {
> > -	pinctrl-names = "default";
> > -	pinctrl-0 = <&pinctrl_hog>;
> > -
> >  	pinctrl_enet1: enet1grp {
> >  		fsl,pins = <
> >  			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
> > @@ -97,13 +102,6 @@ MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
> >  		>;
> >  	};
> >
> > -	pinctrl_hog: hoggrp {
> > -		fsl,pins = <
> > -			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* BT Enable */
> > -			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x03029	/* WLAN Enable */
> > -		>;
> > -	};
> > -
> >  	pinctrl_i2c1: i2c1grp {
> >  		fsl,pins = <
> >  			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
> > new file mode 100644
> > index 0000000000000..519250b31db24
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
> > @@ -0,0 +1,18 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> > + * Variscite SoM mounted on it (6UL CPU variant).
> > + *
> > + * Copyright 2026 Dimonoff
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx6ul-var-som.dtsi"
> > +#include "imx6ul-var-som-concerto-common.dtsi"
> > +#include "imx6ul-var-som-wifi.dtsi"
> > +
> > +/ {
> > +	model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
> > +	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
> > +};
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
> > new file mode 100644
> > index 0000000000000..6d16ff7909dab
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
> > @@ -0,0 +1,75 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Support optional Wifi/Bluetooth on Variscite VAR-SOM-6UL module.
> > + *
> > + * Copyright 2019-2024 Variscite Ltd.
> > + * Copyright 2026 Dimonoff
> > + */
> > +
> > +/ {
> > +	reg_sd1_vmmc: regulator_sd1_vmmc {
> > +		compatible = "regulator-fixed";
> > +		regulator-name = "VMMC1";
> > +		regulator-min-microvolt = <3300000>;
> > +		regulator-max-microvolt = <3300000>;
> > +		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
> > +		enable-active-high;
> > +		startup-delay-us = <10000>;
> > +	};
> > +
> > +	usdhc1_pwrseq: usdhc1-pwrseq {
> > +		compatible = "mmc-pwrseq-simple";
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&pinctrl_brcm_wifi>;
> > +		reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
> > +	};
> > +};
> > +
> > +&iomuxc {
> > +	pinctrl_32k_clk: 32kclkgrp {
> > +		/*
> > +		 * For TP option, an additional oscillator is assembled on the
> > +		 * SOM to provide 32 kHz to the WiFi module. Without TP option,
> > +		 * this pin is configured to provide the 32 KHz clock to the
> > +		 * WiFi module.
> > +		 */
> > +		fsl,pins = <
> > +			MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT	0x03029
> > +		>;
> > +	};
> > +};
> > +
> > +&tsc {
> > +	status = "disabled";
> > +};
> > +
> > +/* Bluetooth UART */
> > +&uart2 {
> > +	bluetooth {
> > +		compatible = "brcm,bcm43438-bt";
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&pinctrl_brcm_bt>;
> > +		shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
> > +		vbat-supply = <&reg_3p3v>;
> > +		vddio-supply = <&reg_3p3v>;
> > +	};
> > +};
> > +
> > +&usdhc1 {
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_32k_clk>;
> > +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_32k_clk>;
> > +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_32k_clk>;
> > +	no-1-8-v;
> > +	non-removable;
> > +	mmc-pwrseq = <&usdhc1_pwrseq>;
> > +	vmmc-supply = <&reg_sd1_vmmc>;
> > +	status = "okay";
> > +
> > +	brcmf: wifi@1 {
> > +		compatible = "brcm,bcm4329-fmac"; /* LWB option: Sterling LWB5 */
> > +		reg = <1>;
> > +	};
> > +};
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
> > index 35a0c0b3603fd..b4e6a9316dd81 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
> > @@ -15,3 +15,18 @@ / {
> >  	model = "Variscite VAR-SOM-6UL module";
> >  	compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
> >  };
> > +
> > +&iomuxc {
> > +	pinctrl_brcm_bt: brcm-bt-grp {
> > +		fsl,pins = <
> > +			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* BT_REG_ON (BT_EN) */
> > +		>;
> > +	};
> > +
> > +	pinctrl_brcm_wifi: brcm-wifi-grp {
> > +		fsl,pins = <
> > +			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0	/* WL_PWR (WIFI_PWR 5G) */
> > +			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x1b0b0	/* WL_REG_ON (WIFI_EN) */
> > +		>;
> > +	};
> > +};
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
> > new file mode 100644
> > index 0000000000000..7c0e313603630
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
> > @@ -0,0 +1,18 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
> > + * Variscite SoM mounted on it (6ULL CPU variant).
> > + *
> > + * Copyright 2026 Dimonoff
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx6ull-var-som.dtsi"
> > +#include "imx6ul-var-som-concerto-common.dtsi"
> > +#include "imx6ul-var-som-wifi.dtsi"
> > +
> > +/ {
> > +	model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
> > +	compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull";
> > +};
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
> > index ba482a97623b2..3067ff6a1bc74 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
> > @@ -13,3 +13,18 @@ / {
> >  	model = "Variscite VAR-SOM-6UL module";
> >  	compatible = "variscite,var-som-imx6ull", "fsl,imx6ull";
> >  };
> > +
> > +&iomuxc {
> > +	pinctrl_brcm_bt: brcm-bt-grp {
> > +		fsl,pins = <
> > +			MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* BT_REG_ON (BT_EN) */
> > +		>;
> > +	};
> > +
> > +	pinctrl_brcm_wifi: brcm-wifi-grp {
> > +		fsl,pins = <
> > +			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0	/* WL_PWR (WIFI_PWR 5G) */
> > +			MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x1b0b0	/* WL_REG_ON (WIFI_EN) */
> > +		>;
> > +	};
> > +};
> > --
> > 2.47.3
> >
> 


-- 
Hugo Villeneuve

Claude review: var-som-6ul: improve support for variants

[Claude Code Review Bot]

Overall Series Review

Subject: var-som-6ul: improve support for variants
Author: Hugo Villeneuve <hugo@hugovil.com>
Patches: 23
Reviewed: 2026-03-03T12:58:05.042886

---

This is a 14-patch series that improves device tree support for the Variscite VAR-SOM-6UL boards. The first few patches fix genuine DT warnings, then the bulk of the series refactors the existing monolithic DTS files into modular DTSI includes (SD, WiFi, ENET1, ENET2, audio, LVDS) and adds imx6ull CPU variant support. The refactoring direction is reasonable, but there are several technical issues:

1. **Critical**: The imx6ull variant files put `MX6ULL_PAD_SNVS_TAMPER*` pads under `&iomuxc` when they must go under `&iomuxc_snvs` on the imx6ull.
2. **Significant**: The ENET1/ENET2 factoring creates a hard dependency where enet1.dtsi can only work if enet2.dtsi is included first, which the author acknowledges but should be resolved.
3. **Significant**: Duplicate `ethphy0` node definitions across enet1.dtsi and enet2.dtsi.
4. The compatible string naming in patch 13 is inconsistent between commit message and code.
5. The LVDS panel node placement in concerto-common means even boards without LVDS get an orphan panel node.

The series would benefit from being split: fixes (1-2) separate from the refactoring/new-features (3-14), as the fixes target stable while the refactoring does not.

---

---
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Claude review: ARM: dts: imx6ul-var-som: fix warning for non-existent dc-supply property

[Claude Code Review Bot]

Patch Review

Straightforward fix removing a non-existent `dc-supply` property from the `cpu@0` node. The Fixes tag and stable CC are appropriate. No issues.

---
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Claude review: ARM: dts: imx6ul-var-som: fix warning for boolean property with a value

[Claude Code Review Bot]

Patch Review

Correct fix: `micrel,rmii-reference-clock-select-25-mhz` is a boolean property and should not have `= <1>`. However, this patch is missing a Fixes tag and `Cc: stable@kernel.org`, unlike patch 1 which is a similar DT warning fix. Consider adding:
```
Fixes: 9d6a67d9c7a9 ("ARM: dts: imx6ul: Add Variscite VAR-SOM-MX6UL SoM support")
Cc: stable@kernel.org
```

---
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Claude review: ARM: dts: imx6ul-var-som: change incorrect VAR-SOM-6UL model name

[Claude Code Review Bot]

Patch Review

Trivial naming fix: `VAR-SOM-MX6UL` -> `VAR-SOM-6UL`. No technical concerns. Might want a Fixes tag since it corrects factual incorrectness from the original commit.

---
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Claude review: dt-bindings: arm: fsl: change incorrect VAR-SOM-6UL model name

[Claude Code Review Bot]

Patch Review

Binding companion to patch 3. Fine as-is.

---
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Claude review: dt-bindings: arm: fsl: add variscite,var-som-imx6ull

[Claude Code Review Bot]

Patch Review

Adds dt-binding entries for the imx6ull concerto variant. Looks correct.

---
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Claude review: ARM: dts: imx6ul-var-som: Factor out common parts for all CPU variants

[Claude Code Review Bot]

Patch Review

Creates `imx6ul-var-som-common.dtsi` from the existing `imx6ul-var-som.dtsi` and a new `imx6ull-var-som.dtsi`. The factoring is mechanically correct. One minor note:

The `imx6ul-var-som-common.dtsi` drops `/dts-v1/;` and the `#include "imx6ul.dtsi"` which is correct for a dtsi that will be included by CPU-variant-specific files.

---
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Claude review: ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU variants

[Claude Code Review Bot]

Patch Review

Creates `imx6ul-var-som-concerto-common.dtsi` and `imx6ull-var-som-concerto.dts`. The `pinctrl_i2c1` definition is moved from concerto-common to var-som-common, which is appropriate since it's SOM-level hardware.

The model string change to include "(6UL CPU)" / "(6ULL CPU)" is a visible ABI change for userspace tools that parse `/proc/device-tree/model`. Might want to call that out explicitly.

---
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Claude review: ARM: dts: imx6ul-var-som: factor out SD card support

[Claude Code Review Bot]

Patch Review

Factors SD card into `imx6ul-var-som-sd.dtsi`. The `pinctrl_usdhc1*` definitions are moved to `imx6ul-var-som-common.dtsi` while the SD-specific GPIO CD pin and the `&usdhc1` configuration go into the SD-specific dtsi. This makes sense since the same USDHC1 pins are shared between SD and WiFi.

The `pinctrl_usdhc1_gpio` with the CD pin staying in the sd.dtsi is correct since WiFi uses don't need the CD pin.

---
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Claude review: ARM: dts: imx6ul-var-som: add proper Wifi and Bluetooth support

[Claude Code Review Bot]

Patch Review

**Issue 1 (Critical)**: In `imx6ull-var-som.dtsi`, the `MX6ULL_PAD_SNVS_TAMPER*` pads are placed under `&iomuxc`:

```c
&iomuxc {
    pinctrl_brcm_bt: brcm-bt-grp {
        fsl,pins = <
            MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04  0x1b0b0
        >;
    };
    pinctrl_brcm_wifi: brcm-wifi-grp {
        fsl,pins = <
            MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02  0x1b0b0
            MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06  0x1b0b0
        >;
    };
};
```

On the imx6ull, the SNVS tamper pads belong to the separate `iomuxc_snvs` controller (defined in `imx6ull.dtsi` at `pinctrl@2290000`). All other imx6ull device trees in the kernel tree correctly use `&iomuxc_snvs` for these pads. This should be:

```c
&iomuxc_snvs {
    pinctrl_brcm_bt: ...
    pinctrl_brcm_wifi: ...
};
```

**Issue 2**: The `reg_sd1_vmmc` node name uses underscores:
```
reg_sd1_vmmc: regulator_sd1_vmmc {
```
DT naming convention prefers hyphens: `regulator-sd1-vmmc`.

**Issue 3**: The `imx6ul-var-som-wifi.dtsi` uses `GPIO_ACTIVE_HIGH` and `GPIO_ACTIVE_LOW` macros but doesn't include `<dt-bindings/gpio/gpio.h>`. It works because it's always included after files that already include it, but it's fragile. Consider adding the include.

**Issue 4**: The "full" naming convention (e.g., `imx6ul-var-som-concerto-full.dts`) is unconventional for upstream kernel DTS files. Typically DT variants are named for the specific option they enable. Something like `imx6ul-var-som-concerto-wifi.dts` might be more descriptive, or the approach used by other boards with board-level overlays.

---
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Claude review: ARM: dts: imx6ul-var-som: factor out ENET2 ethernet support

[Claude Code Review Bot]

Patch Review

The `rmii_ref_clk` fixed-clock is correctly moved into `imx6ul-var-som-enet2.dtsi` since it's only needed by ethernet. The ENET2 configuration and pinctrl are cleanly factored out. No issues with this patch in isolation.

---
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Claude review: ARM: dts: imx6ul-var-som: add support for EC configuration option (ENET1)

[Claude Code Review Bot]

Patch Review

**Issue 1 (Critical, same as patch 9)**: The `pinctrl_enet1_gpio` in `imx6ull-var-som.dtsi` uses `MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00` under `&iomuxc` — this must be `&iomuxc_snvs`.

**Issue 2 (Significant)**: There is a duplicate definition of `ethphy0: ethernet-phy@1` — it appears in both `imx6ul-var-som-enet2.dtsi` (added by this patch) and `imx6ul-var-som-enet1.dtsi`. When both are included in the `-full` boards, the same node is defined twice with the same label at the same path. While DTS merge semantics allow this (properties get overwritten with identical values), it is confusing and error-prone.

A cleaner approach would be to have `ethphy0` defined only in `enet1.dtsi` (since it's the ENET1 PHY), and use the `mdio_enet2` label from enet2.dtsi to place it. Don't duplicate it in enet2.dtsi.

**Issue 3 (Significant)**: The author acknowledges the design problem in the `---` notes:
> In order for this to work, imx6ul-var-som-enet2.dtsi must be included first, and thus enabled, even if not used. Maybe there is a better way to support both independently, but I'm not sure how.

This forced dependency on enet2.dtsi for enet1 to work is fragile. Consider defining the shared MDIO bus in the common dtsi or in a separate shared file, rather than making enet1 depend on enet2's internal implementation.

**Issue 4**: The `pinctrl_enet1_mdio` group from the original code was dropped. The original had:
```c
pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
```
The new version has:
```c
pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>;
```
This seems intentional since fec1 now uses fec2's MDIO bus, but should be noted in the commit message.

---
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Claude review: ARM: dts: imx6ul-var-som: factor out audio support

[Claude Code Review Bot]

Patch Review

Clean factoring of SAI2 audio into `imx6ul-var-som-audio.dtsi`. No issues.

---
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Claude review: dt-bindings: display/lvds-codec: add ti,sn65lvds93

[Claude Code Review Bot]

Patch Review

**Issue**: The commit message says "SN65LVDS93" but the code uses `ti,sn75lvds93`. Looking at TI's product line, the SN**75**LVDS83/93 are the FlatLink transmitters (encoders), while the SN**65**LVDS series are receivers. Since this is in the encoder section of the binding, `sn75lvds93` in the code is correct, but the commit message and subject should say "sn75lvds93" not "sn65lvds93":

```
Subject: dt-bindings: display/lvds-codec: add ti,sn75lvds93
                                              ^^
```

Also, the commit description says "Similar to SN65LVDS83" — should be "SN75LVDS83".

---
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Claude review: ARM: dts: imx6ul-var-som: add support for LVDS display panel

[Claude Code Review Bot]

Patch Review

**Issue 1**: The `lvds_panel` node is defined in `imx6ul-var-som-concerto-common.dtsi`, meaning every concerto board (even without LVDS) gets this panel node with timings. It would be cleaner to define the entire panel in `imx6ul-var-som-lvds-panel.dtsi`.

**Issue 2**: The panel node lacks a `backlight = <&lcd_backlight>;` property. Without it, the backlight won't be automatically controlled by the DRM panel subsystem.

**Issue 3**: The `pwm-names` property is unusual:
```
pwm-names = "LCD_BKLT_PWM";
```
The `pwm-backlight` driver doesn't use `pwm-names` and this value serves no purpose. Either drop it or use the conventional lowercase naming.

**Issue 4**: `status = "okay"` on the backlight node is redundant for a root-level node.

**Issue 5**: The commit message has a typo — missing space: "optionso" should be "option, so".

**Issue 6**: The `lcdif_dat` pinctrl only configures 18 data pins (skipping DATA00-01, DATA08-09, DATA16-17), consistent with JEIDA-18 mapping. This looks intentional for the 18-bit LVDS encoder, which is correct.

---
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