[PATCH 0/4] Add RZ/G3L GFX support

[PATCH 0/4] Add RZ/G3L GFX support

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The Renesas RZ/G3L SoC includes the Arm Mali-G31 GPU as a 3D Graphics
Engine (GE3D). The Arm Mali-G31 GPU is a graphics acceleration platform
that is based on open standards. It supports 2D graphics, 3D graphics, and
General Purpose computing on GPU (GPGPU). Add the binding and driver
support for suspend/resume functionality along with some improvements in
panfrost driver.

Biju Das (4):
  dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3L SoC
  drm/panfrost: Drop redundant optional clock checks in runtime PM
  drm/panfrost: Add bus_ace optional clock support for RZ/G2L
  drm/panfrost: Add GPU_PM_RT support for RZ/G3L SoC

 .../bindings/gpu/arm,mali-bifrost.yaml        |  2 ++
 drivers/gpu/drm/panfrost/panfrost_device.c    | 36 ++++++++++++++-----
 drivers/gpu/drm/panfrost/panfrost_device.h    |  1 +
 drivers/gpu/drm/panfrost/panfrost_drv.c       |  1 +
 4 files changed, 32 insertions(+), 8 deletions(-)

-- 
2.43.0

[PATCH 1/4] dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3L SoC

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add a compatible string for the Renesas RZ/G3L SoC variants that include a
Mali-G31 GPU. These variants share the same restrictions on interrupts,
clocks, and power domains as the RZ/G2L SoC, so extend the existing schema
validation accordingly.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index db49b8ff8c74..9db9f84ad964 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -26,6 +26,7 @@ properties:
               - realtek,rtd1619-mali
               - renesas,r9a07g044-mali
               - renesas,r9a07g054-mali
+              - renesas,r9a08g046-mali
               - renesas,r9a09g047-mali
               - renesas,r9a09g056-mali
               - renesas,r9a09g057-mali
@@ -150,6 +151,7 @@ allOf:
             enum:
               - renesas,r9a07g044-mali
               - renesas,r9a07g054-mali
+              - renesas,r9a08g046-mali
               - renesas,r9a09g047-mali
               - renesas,r9a09g056-mali
               - renesas,r9a09g057-mali
-- 
2.43.0

Claude review: dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3L SoC

[Claude Code Review Bot]

Patch Review

This patch adds `renesas,r9a08g046-mali` to the mali-bifrost binding in two places: the compatible enum and the allOf conditional that constrains interrupts/clocks/power-domains for Renesas SoCs.

**Looks correct.** The new compatible is placed in alphabetical order alongside the existing Renesas entries and added to both the top-level compatible list and the allOf constraint block. No issues.

---
Generated by Claude Code Patch Reviewer

[PATCH 2/4] drm/panfrost: Drop redundant optional clock checks in runtime PM

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The clk_enable() and clk_disable() APIs already handle NULL clock pointers
gracefully — clk_enable() returns 0 and clk_disable() returns immediately
when passed a NULL or optional clock. The explicit if (pfdev->bus_clock)
guards around these calls in the runtime suspend/resume paths are
therefore unnecessary. Remove them to simplify the code.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/gpu/drm/panfrost/panfrost_device.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
index dedc13e56631..01e702a0b2f0 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -429,11 +429,9 @@ static int panfrost_device_runtime_resume(struct device *dev)
 		if (ret)
 			goto err_clk;
 
-		if (pfdev->bus_clock) {
-			ret = clk_enable(pfdev->bus_clock);
-			if (ret)
-				goto err_bus_clk;
-		}
+		ret = clk_enable(pfdev->bus_clock);
+		if (ret)
+			goto err_bus_clk;
 	}
 
 	panfrost_device_reset(pfdev, true);
@@ -464,9 +462,7 @@ static int panfrost_device_runtime_suspend(struct device *dev)
 	panfrost_gpu_power_off(pfdev);
 
 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) {
-		if (pfdev->bus_clock)
-			clk_disable(pfdev->bus_clock);
-
+		clk_disable(pfdev->bus_clock);
 		clk_disable(pfdev->clock);
 		reset_control_assert(pfdev->rstc);
 	}
-- 
2.43.0

Claude review: drm/panfrost: Drop redundant optional clock checks in runtime PM

[Claude Code Review Bot]

Patch Review

This patch removes the `if (pfdev->bus_clock)` guards around `clk_enable()`/`clk_disable()` calls in the runtime PM paths. The commit message correctly notes that the clk API handles NULL pointers gracefully.

**Looks correct.** This is a straightforward cleanup. The `clk_enable()` and `clk_disable()` APIs are indeed NULL-safe. Removing the guards simplifies the code and makes Patch 3 cleaner.

---
Generated by Claude Code Patch Reviewer

[PATCH 3/4] drm/panfrost: Add bus_ace optional clock support for RZ/G2L

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

On RZ/G2L SoCs, the GPU MMU requires a bus_ace clock to operate correctly.
Without it, unbind/bind cycles leave the GPU non-operational, manifesting
as an AS_ACTIVE bit stuck and a soft reset timeout falling back to hard
reset. Add bus_ace_clock as an optional clock, wiring it into init/fini,
and the runtime suspend/resume paths alongside the existing optional
bus_clock.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/gpu/drm/panfrost/panfrost_device.c | 24 ++++++++++++++++++++++
 drivers/gpu/drm/panfrost/panfrost_device.h |  1 +
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
index 01e702a0b2f0..87dae0ed748a 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -70,8 +70,23 @@ static int panfrost_clk_init(struct panfrost_device *pfdev)
 			goto disable_clock;
 	}
 
+	pfdev->bus_ace_clock = devm_clk_get_optional(pfdev->base.dev, "bus_ace");
+	if (IS_ERR(pfdev->bus_ace_clock)) {
+		err = PTR_ERR(pfdev->bus_ace_clock);
+		dev_err(pfdev->base.dev, "get bus_ace_clock failed %ld\n",
+			PTR_ERR(pfdev->bus_ace_clock));
+		err = PTR_ERR(pfdev->bus_ace_clock);
+		goto disable_bus_clock;
+	}
+
+	err = clk_prepare_enable(pfdev->bus_ace_clock);
+	if (err)
+		goto disable_bus_clock;
+
 	return 0;
 
+disable_bus_clock:
+	clk_disable_unprepare(pfdev->bus_clock);
 disable_clock:
 	clk_disable_unprepare(pfdev->clock);
 
@@ -80,6 +95,7 @@ static int panfrost_clk_init(struct panfrost_device *pfdev)
 
 static void panfrost_clk_fini(struct panfrost_device *pfdev)
 {
+	clk_disable_unprepare(pfdev->bus_ace_clock);
 	clk_disable_unprepare(pfdev->bus_clock);
 	clk_disable_unprepare(pfdev->clock);
 }
@@ -432,6 +448,10 @@ static int panfrost_device_runtime_resume(struct device *dev)
 		ret = clk_enable(pfdev->bus_clock);
 		if (ret)
 			goto err_bus_clk;
+
+		ret = clk_enable(pfdev->bus_ace_clock);
+		if (ret)
+			goto err_bus_ace_clk;
 	}
 
 	panfrost_device_reset(pfdev, true);
@@ -439,6 +459,9 @@ static int panfrost_device_runtime_resume(struct device *dev)
 
 	return 0;
 
+err_bus_ace_clk:
+	if (pfdev->comp->pm_features & BIT(GPU_PM_RT))
+		clk_disable(pfdev->bus_clock);
 err_bus_clk:
 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT))
 		clk_disable(pfdev->clock);
@@ -462,6 +485,7 @@ static int panfrost_device_runtime_suspend(struct device *dev)
 	panfrost_gpu_power_off(pfdev);
 
 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) {
+		clk_disable(pfdev->bus_ace_clock);
 		clk_disable(pfdev->bus_clock);
 		clk_disable(pfdev->clock);
 		reset_control_assert(pfdev->rstc);
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
index 0f3992412205..ec55c136b1b6 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -136,6 +136,7 @@ struct panfrost_device {
 	void __iomem *iomem;
 	struct clk *clock;
 	struct clk *bus_clock;
+	struct clk *bus_ace_clock;
 	struct regulator_bulk_data *regulators;
 	struct reset_control *rstc;
 	/* pm_domains for devices with more than one. */
-- 
2.43.0

Claude review: drm/panfrost: Add bus_ace optional clock support for RZ/G2L

[Claude Code Review Bot]

Patch Review

This patch adds a `bus_ace_clock` optional clock, wiring it into init, fini, and runtime suspend/resume.

**Bug: Duplicate `err = PTR_ERR(...)` assignment.** In `panfrost_clk_init()`:

```c
+	if (IS_ERR(pfdev->bus_ace_clock)) {
+		err = PTR_ERR(pfdev->bus_ace_clock);
+		dev_err(pfdev->base.dev, "get bus_ace_clock failed %ld\n",
+			PTR_ERR(pfdev->bus_ace_clock));
+		err = PTR_ERR(pfdev->bus_ace_clock);
+		goto disable_bus_clock;
+	}
```

The `err = PTR_ERR(pfdev->bus_ace_clock)` is assigned twice (lines before and after the `dev_err`). This is harmless but clearly a copy-paste error. The first assignment should be removed (keeping it after `dev_err` for consistency with the existing `bus_clock` error block pattern), or the second one removed.

**Inconsistency with bus_clock init pattern.** The existing `bus_clock` init code has a `if (pfdev->bus_clock)` guard around `clk_prepare_enable()` (line 64-71 in the applied code), which also prints the clock rate. The new `bus_ace_clock` code calls `clk_prepare_enable()` unconditionally (which is fine since the clk API handles NULL), but this creates an inconsistency within the same function. Consider either: (a) also removing the NULL guard from the `bus_clock` block for consistency, or (b) matching the existing pattern. This is minor since the API handles NULL, but consistency aids readability.

**Runtime resume error path nesting.** The `clk_enable(pfdev->bus_ace_clock)` call and its error label `err_bus_ace_clk` are placed *inside* the `if (pfdev->comp->pm_features & BIT(GPU_PM_RT))` block, but the error label itself is *outside* the block:

```c
	if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) {
		...
		ret = clk_enable(pfdev->bus_ace_clock);
		if (ret)
			goto err_bus_ace_clk;
	}
	...
	return 0;

err_bus_ace_clk:
	if (pfdev->comp->pm_features & BIT(GPU_PM_RT))
		clk_disable(pfdev->bus_clock);
```

This works because the goto only fires when `GPU_PM_RT` is set, and the error handlers re-check the flag. This matches the existing pattern for `err_bus_clk` and `err_clk`, so it's fine.

---
Generated by Claude Code Patch Reviewer

[PATCH 4/4] drm/panfrost: Add GPU_PM_RT support for RZ/G3L SoC

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

RZ/G3L SoC is embedded with Mali-G31 GPU system. Add GPU_PM_RT support as
it needs to be assert/deassert the reset during suspend/resume.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/gpu/drm/panfrost/panfrost_drv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index 711f5101aa04..3d0bdba2a474 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -1156,6 +1156,7 @@ static const struct of_device_id dt_match[] = {
 	  .data = &amlogic_data, },
 	{ .compatible = "amlogic,meson-g12a-mali",
 	  .data = &amlogic_data, },
+	{ .compatible = "renesas,r9a08g046-mali", .data = &default_pm_rt_data },
 	{ .compatible = "renesas,r9a09g047-mali", .data = &default_pm_rt_data },
 	{ .compatible = "arm,mali-t604", .data = &default_data, },
 	{ .compatible = "arm,mali-t624", .data = &default_data, },
-- 
2.43.0

Claude review: drm/panfrost: Add GPU_PM_RT support for RZ/G3L SoC

[Claude Code Review Bot]

Patch Review

This patch adds a single compatible entry `renesas,r9a08g046-mali` pointing to `default_pm_rt_data`.

**Looks correct.** The placement is alphabetically ordered next to the existing `r9a09g047` entry. The `default_pm_rt_data` provides `GPU_PM_RT` which ensures the reset assert/deassert and clock enable/disable happen during runtime suspend/resume, matching the cover letter's description.

**Minor: The commit message says "RZ/G3L SoC" but doesn't mention which GPU it has.** The cover letter states it's a Mali-G31, and this is a bifrost driver entry, so it's fine, but the commit message could be slightly more descriptive.

---

**Summary of required changes:**
1. **Patch 3**: Remove the duplicate `err = PTR_ERR(pfdev->bus_ace_clock)` assignment — this is a clear copy-paste bug.

**Optional improvements:**
- **Patch 3**: Harmonize the `bus_clock` init code with the `bus_ace_clock` init code (either both guarded or both unguarded for `clk_prepare_enable`).

---
Generated by Claude Code Patch Reviewer

Claude review: Add RZ/G3L GFX support

[Claude Code Review Bot]

Overall Series Review

Subject: Add RZ/G3L GFX support
Author: Biju <biju.das.au@gmail.com>
Patches: 5
Reviewed: 2026-03-05T13:22:26.862247

---

This is a 4-patch series adding GPU support for the Renesas RZ/G3L SoC (which has a Mali-G31). The series is well-structured: DT binding first, a cleanup patch, a new clock addition, and finally the SoC-specific compatible entry. The changes are straightforward and low-risk. There is one clear bug (duplicate assignment) and one structural inconsistency worth addressing.

---
Generated by Claude Code Patch Reviewer