From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6006FEF8FEA for ; Wed, 4 Mar 2026 13:48:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B791E10EA0B; Wed, 4 Mar 2026 13:48:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="dotWWyMG"; dkim-atps=neutral Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 071E310EA0B for ; Wed, 4 Mar 2026 13:48:51 +0000 (UTC) Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-439c944bb62so495494f8f.3 for ; Wed, 04 Mar 2026 05:48:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772632129; x=1773236929; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QTTqK7TuaDqF+tP6hPwnkWAR5TFFHKJ4XYpEBPBHnmY=; b=dotWWyMGwLT/1gHWrBIuERsPzDeSYMw0Bs7BFixDqjz9I/8e1nUhvSQq2Uf203OKN8 VCFyiPAwYEoyMFW1XkhZViH3+aVderkONWgrf7bbQZnoaNUAfajEpVlysyRwnsBX9eiJ QC65px5Snwm+8R/YP3LpOFY06el9vsAiQVf47FfmQBN9FfjkPHqNF/TgIhJdMIXuLywG TXaRj297G8/p1NtMH1Q7d4mEDucrxCuUfkeEwX41lafp0YJTh6St8tpPWlOTE9Ll1pPz k8Iy07IpMbkogFBgJyiAEPjtB2slZ5jnN2PD5zdY+OjDNritkbL26LLXUSrA+cY/zEi7 GX2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772632129; x=1773236929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=QTTqK7TuaDqF+tP6hPwnkWAR5TFFHKJ4XYpEBPBHnmY=; b=FFutBmjwlWWfxiGLYGPEunxeaiRGj0xJqN83fbgVMWINraffpOKF2FIZny8n8EvVzE 6qdR7gEdfJGSe2ISIXMP7ffaN1JtaJtdNp0oCnPUY8bhEBOHX7LenxPfRDdww+M0WBFk j0xfdTK3GiINp9QRZncNbr0KlnV//GS05Byl4uyHw6uAsjxUGnhJ5MdxgD8SlAbiu4uU JdRIVPKUQSn+h0l7idMHvTU1n2jxrO40HnGVt1iIjttXr9rqTkihpHs93Fqtpgop6AlC HREIdQYlLMUoJTYEJe6ha6RF5bqF/XW3VyjoV9eViF9FhuWpsSm/m8+xs1OUT3R3fqnH 2YCw== X-Forwarded-Encrypted: i=1; AJvYcCW4yFj06P16DbNcFbRkXxzd4bWCsQgSO7z4I3E3EAvs4lhMyi6V5Iwq3lxQhuYBE/nUc5gf7TMFW5Y=@lists.freedesktop.org X-Gm-Message-State: AOJu0YwN56EEUTu34VMz81lh0VBAYsYni68TfgZ9HpTKXikCSsHe9TWU lKiBmokKiDnLj/IlVKM/oc4OCf4znbqiRcibkiQ31eCaRWN/dW//8HfF X-Gm-Gg: ATEYQzxPoGiaNDsgzmXuhMmJFF4GDCAHqlDSLslYaEWKG3065gFFWH91FKxzHPwrGB5 f496owROCkiWNS8fZzKadzMUyzRejMjgMQ7p4R6ZVQ1I4GrNE2YcwIq2kttckIIz/xQ42BpaFDu f96X/qyclSCoiXusXGK/sP0Vbk/I2iM5vYXBjA92Jjdw/1EEgUoDz82e7yrczsHPLPKXbkiMlIm 3k37bY0WYrvfrJt+XVaHj9umLoYtqT7sjE1W5EUpa7iGPDjyAnj4ct0PkYaUSqPHN1jSLDoLb2g 21B9oWSrxut5DRVcwSsUhwrsrchANGxGAd6OnOJic9zVqpdAGeTx+ooGzTUjLPSR8+8mySazsCV duUu4HZKg33lg3p2GyvJGtSP0fYcYFBrd6AcF+9XH54yP+F7sXJb/9iANUmmbbUWpxb24srsZ92 4N2MJQG4ms4EmYDiSjvSW/49XpqZf3GzU= X-Received: by 2002:a05:6000:2891:b0:439:b3d2:3766 with SMTP id ffacd0b85a97d-439c7fae450mr3798988f8f.19.1772632129397; Wed, 04 Mar 2026 05:48:49 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:de3f:f927:40ff:12a6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439c65e0b23sm7105229f8f.32.2026.03.04.05.48.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 05:48:49 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Boris Brezillon , Rob Herring , Steven Price , =?UTF-8?q?Adri=C3=A1n=20Larumbe?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Biju Das , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 3/4] drm/panfrost: Add bus_ace optional clock support for RZ/G2L Date: Wed, 4 Mar 2026 13:48:38 +0000 Message-ID: <20260304134845.267030-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260304134845.267030-1-biju.das.jz@bp.renesas.com> References: <20260304134845.267030-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Biju Das On RZ/G2L SoCs, the GPU MMU requires a bus_ace clock to operate correctly. Without it, unbind/bind cycles leave the GPU non-operational, manifesting as an AS_ACTIVE bit stuck and a soft reset timeout falling back to hard reset. Add bus_ace_clock as an optional clock, wiring it into init/fini, and the runtime suspend/resume paths alongside the existing optional bus_clock. Signed-off-by: Biju Das --- drivers/gpu/drm/panfrost/panfrost_device.c | 24 ++++++++++++++++++++++ drivers/gpu/drm/panfrost/panfrost_device.h | 1 + 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c index 01e702a0b2f0..87dae0ed748a 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -70,8 +70,23 @@ static int panfrost_clk_init(struct panfrost_device *pfdev) goto disable_clock; } + pfdev->bus_ace_clock = devm_clk_get_optional(pfdev->base.dev, "bus_ace"); + if (IS_ERR(pfdev->bus_ace_clock)) { + err = PTR_ERR(pfdev->bus_ace_clock); + dev_err(pfdev->base.dev, "get bus_ace_clock failed %ld\n", + PTR_ERR(pfdev->bus_ace_clock)); + err = PTR_ERR(pfdev->bus_ace_clock); + goto disable_bus_clock; + } + + err = clk_prepare_enable(pfdev->bus_ace_clock); + if (err) + goto disable_bus_clock; + return 0; +disable_bus_clock: + clk_disable_unprepare(pfdev->bus_clock); disable_clock: clk_disable_unprepare(pfdev->clock); @@ -80,6 +95,7 @@ static int panfrost_clk_init(struct panfrost_device *pfdev) static void panfrost_clk_fini(struct panfrost_device *pfdev) { + clk_disable_unprepare(pfdev->bus_ace_clock); clk_disable_unprepare(pfdev->bus_clock); clk_disable_unprepare(pfdev->clock); } @@ -432,6 +448,10 @@ static int panfrost_device_runtime_resume(struct device *dev) ret = clk_enable(pfdev->bus_clock); if (ret) goto err_bus_clk; + + ret = clk_enable(pfdev->bus_ace_clock); + if (ret) + goto err_bus_ace_clk; } panfrost_device_reset(pfdev, true); @@ -439,6 +459,9 @@ static int panfrost_device_runtime_resume(struct device *dev) return 0; +err_bus_ace_clk: + if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) + clk_disable(pfdev->bus_clock); err_bus_clk: if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) clk_disable(pfdev->clock); @@ -462,6 +485,7 @@ static int panfrost_device_runtime_suspend(struct device *dev) panfrost_gpu_power_off(pfdev); if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) { + clk_disable(pfdev->bus_ace_clock); clk_disable(pfdev->bus_clock); clk_disable(pfdev->clock); reset_control_assert(pfdev->rstc); diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h index 0f3992412205..ec55c136b1b6 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -136,6 +136,7 @@ struct panfrost_device { void __iomem *iomem; struct clk *clock; struct clk *bus_clock; + struct clk *bus_ace_clock; struct regulator_bulk_data *regulators; struct reset_control *rstc; /* pm_domains for devices with more than one. */ -- 2.43.0