From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3741FCC046 for ; Fri, 6 Mar 2026 17:18:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 489B910E3EE; Fri, 6 Mar 2026 17:18:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FEQB9/yJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id D3C2D10E3E4; Fri, 6 Mar 2026 17:18:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772817527; x=1804353527; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hDlEWA9Oj6QJGdF7mai92XU2DhfM3LKNWqF7MrQ6isk=; b=FEQB9/yJdGRr2SZNs+SA9IrJJhWf+gZ3SaoOT6qEOrPXmrrtCxXyE4cB Y+Wz7qUGtcxoJKcDAf4onBAyk69poV2OFwafCkGrofkLwBg8g3ja9ScxJ JZ02/tPabJsrCP4AciRCQwy3O8uj914gYrBUZpoxkacyUno4c4yEPiAyS QadYkuY59O5KMO1tvVXB9LzTq/oLqzkfXUB3TWwHVo0LS/IjnK52WfE3q Vn1MJz9W9K+eDbzs8ibuVHx0j12GcEEGhJJcsms2q2lsqhOpS6FszcvVl HoAQ1567W4KClmu6IdhvfGfEENzxo5FE/mX5PfUjBAopop4AoxeJ7zHx6 g==; X-CSE-ConnectionGUID: 7Kkdt8F4SP60gJxKiy6p+g== X-CSE-MsgGUID: WyZz1HMaRsu7xfhEAs7fBg== X-IronPort-AV: E=McAfee;i="6800,10657,11721"; a="77530692" X-IronPort-AV: E=Sophos;i="6.23,105,1770624000"; d="scan'208";a="77530692" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2026 09:18:46 -0800 X-CSE-ConnectionGUID: 8CX53VC1SwSydJadkyzHfA== X-CSE-MsgGUID: Scv1bbUMTMytemvp6GVkug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,105,1770624000"; d="scan'208";a="216175022" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa010.fm.intel.com with ESMTP; 06 Mar 2026 09:18:41 -0800 From: Chaitanya Kumar Borah To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: harry.wentland@amd.com, louis.chauvet@bootlin.com, mwen@igalia.com, contact@emersion.fr, alex.hung@amd.com, daniels@collabora.com, uma.shankar@intel.com, maarten.lankhorst@intel.com, pekka.paalanen@collabora.com, pranay.samala@intel.com, swati2.sharma@intel.com, Chaitanya Kumar Borah Subject: [PATCH 02/10] drm/i915/color: Add CSC on SDR plane color pipeline Date: Fri, 6 Mar 2026 22:22:59 +0530 Message-Id: <20260306165307.3233194-3-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260306165307.3233194-1-chaitanya.kumar.borah@intel.com> References: <20260306165307.3233194-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the fixed-function CSC block to color pipeline in SDR planes as a DRM_COLOROP_CSC_FF colorop. Signed-off-by: Chaitanya Kumar Borah --- .../drm/i915/display/intel_color_pipeline.c | 22 ++++++++++++++++++- .../drm/i915/display/intel_display_limits.h | 1 + 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c index 6cf8080ee800..f368a896d2fc 100644 --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c @@ -43,6 +43,16 @@ static const enum intel_color_block hdr_plane_pipeline[] = { INTEL_PLANE_CB_POST_CSC_LUT, }; +static const enum intel_color_block sdr_plane_pipeline[] = { + INTEL_PLANE_CB_CSC_FF, +}; + +static const u64 intel_plane_supported_csc_ff = + BIT(DRM_COLOROP_CSC_FF_YUV601_RGB601) | + BIT(DRM_COLOROP_CSC_FF_YUV709_RGB709) | + BIT(DRM_COLOROP_CSC_FF_YUV2020_RGB2020) | + BIT(DRM_COLOROP_CSC_FF_RGB709_RGB2020); + static bool plane_has_3dlut(struct intel_display *display, enum pipe pipe, struct drm_plane *plane) { @@ -92,6 +102,12 @@ struct intel_colorop *intel_color_pipeline_plane_add_colorop(struct drm_plane *p DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR, DRM_COLOROP_FLAG_ALLOW_BYPASS); break; + case INTEL_PLANE_CB_CSC_FF: + ret = drm_plane_colorop_csc_ff_init(dev, &colorop->base, plane, + &intel_colorop_funcs, + intel_plane_supported_csc_ff, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + break; default: drm_err(plane->dev, "Invalid colorop id [%d]", id); ret = -EINVAL; @@ -122,13 +138,17 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en int pipeline_len; int ret = 0; int i; + bool is_hdr = icl_is_hdr_plane(display, to_intel_plane(plane)->id); if (plane_has_3dlut(display, pipe, plane)) { pipeline = xe3plpd_primary_plane_pipeline; pipeline_len = ARRAY_SIZE(xe3plpd_primary_plane_pipeline); - } else { + } else if (is_hdr) { pipeline = hdr_plane_pipeline; pipeline_len = ARRAY_SIZE(hdr_plane_pipeline); + } else { + pipeline = sdr_plane_pipeline; + pipeline_len = ARRAY_SIZE(sdr_plane_pipeline); } for (i = 0; i < pipeline_len; i++) { diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h index 453f7b720815..f4aad54472ce 100644 --- a/drivers/gpu/drm/i915/display/intel_display_limits.h +++ b/drivers/gpu/drm/i915/display/intel_display_limits.h @@ -167,6 +167,7 @@ enum aux_ch { enum intel_color_block { INTEL_PLANE_CB_PRE_CSC_LUT, INTEL_PLANE_CB_CSC, + INTEL_PLANE_CB_CSC_FF, INTEL_PLANE_CB_POST_CSC_LUT, INTEL_PLANE_CB_3DLUT, -- 2.25.1