From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C379EB104F for ; Tue, 10 Mar 2026 11:42:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C88B710E25E; Tue, 10 Mar 2026 11:42:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=imgtec.com header.i=@imgtec.com header.b="sW7wJM9A"; dkim-atps=neutral Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) by gabe.freedesktop.org (Postfix) with ESMTPS id 93BC310E25C for ; Tue, 10 Mar 2026 11:41:58 +0000 (UTC) Received: from pps.filterd (m0168889.ppops.net [127.0.0.1]) by mx07-00376f01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62A5m0dJ2617699; Tue, 10 Mar 2026 11:41:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=S ijKFBgSgJtCfOgUKDJRXuzxQDRnA9W4pWQhssabzt0=; b=sW7wJM9AFcVc5g6Ys ThayJ19zmbX5E/BSqWy7wDIWOJDfgM6O1rZi5BziqW6tVuYFG63w5xNzZCxtH63U pGYOiQx+BLN+zSi7qTWZeCZS0tC6BSN1CKVBF2A6aNBj7XNRM56L6fi4LXisyTCk 0nI66BCbQmEAA+fQu1wdBQmUCwLPdagd4BMDPuQPdmE62PQfNVoWiXsn7j7nv+dm uHqMyCCXe0WXzE2/SCLa9RzXbp7ycpvawQZCLdUShq3O+vr7IMLVOiIdaRJCeg3i 24y1Z/2mhiDAuhW6oIAJHprjFyIuokyDvktfXmYY0Qy7yz6d+FZYYWsaHuyga+JJ kAuuA== Received: from hhmail01.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx07-00376f01.pphosted.com (PPS) with ESMTPS id 4ct3kr8q36-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 10 Mar 2026 11:41:41 +0000 (GMT) Received: from NP-A-BELLE.kl.imgtec.org (172.25.8.171) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Tue, 10 Mar 2026 11:41:40 +0000 From: Alessio Belle Date: Tue, 10 Mar 2026 11:41:12 +0000 Subject: [PATCH 2/2] drm/imagination: Disable interrupts before suspending the GPU MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260310-drain-irqs-before-suspend-v1-2-bf4f9ed68e75@imgtec.com> References: <20260310-drain-irqs-before-suspend-v1-0-bf4f9ed68e75@imgtec.com> In-Reply-To: <20260310-drain-irqs-before-suspend-v1-0-bf4f9ed68e75@imgtec.com> To: Frank Binns , Matt Coster , Brajesh Gupta , "Alexandru Dadu" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: , , "Alessio Belle" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773142899; l=2905; i=alessio.belle@imgtec.com; s=20251208; h=from:subject:message-id; bh=rfcImWO5u1M6GgdhPBmqgLwi5anOe3Jmg2zQkfeUrAo=; b=fqUMI3DCl0PpmNyhvy6RnD5uGu6Dng/YeRjwvR0koR0bhOARrFPJW0Y20+uLDS0itlh12IhEI fyNPDsRv/lnBqMqadIgG4Y36+2d9eB1Erm79ks3iVivqfMUgDjeXbAk X-Developer-Key: i=alessio.belle@imgtec.com; a=ed25519; pk=2Vtuk+GKBRjwMqIHpKk+Gx6zl7cgtq0joszcOc0zF4g= X-Originating-IP: [172.25.8.171] X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDEwMSBTYWx0ZWRfX6H5PP5MKUvr6 IvqmV00Ba1o0rqWw7d5/bdYuiijgkSrycavmtgWm1+6wGzQUjSIE3NO1GXZvH7Pc2FWsbhVMpLE +ytyr9kTmOib5bwLIxb7hf0uFNovruwcJ2IcabR0ypQ+jYxCKj03YHWhtcffi+q8DlnEFL2I58s pEUPJP53cUWV+rlkkOBFWIFWGoIq8bV/Nz2reg5KYoaHZAmaH5PQfD5fnE2cY4BNX2C3sjBziDy U0zKGDJCkhC1pEQrV90qa6JxaquK10TNZ26ZUNdZbaZ7l0fjBqRWPolreB65JolUcFfpyXI3AnV BC0OHhlBc3viMBrxrNi92sTedhj4Rvr6ICen9VqYcWy73N0/eJ/kZnuFSd0VV95p7evSlyCQDvd bVsoeUjWZbo2kYGFwv9AorMkyLj6Tut6DElQhGBu7lwrvaP2bt8DXxbVvqoAYLN397nkOX78d0/ L48IFvV1K33/wUvk/iQ== X-Proofpoint-GUID: f6cPMCgM9sI0iDjosLxUyRTo7wqXtXbM X-Proofpoint-ORIG-GUID: f6cPMCgM9sI0iDjosLxUyRTo7wqXtXbM X-Authority-Analysis: v=2.4 cv=MuhfKmae c=1 sm=1 tr=0 ts=69b00375 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=Rd4DrVCMV_EA:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=kQ-hrUj2-E3RCbRHssb7:22 a=7RYWX5rxfSByPNLylY2M:22 a=r_1tXGB3AAAA:8 a=qGs6vJjZfZ_MceZGOfAA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This is an additional safety layer to ensure no accesses to the GPU registers can be made while it is powered off. While we can disable IRQ generation from GPU, META firmware, MIPS firmware and for safety events, we cannot do the same for the RISC-V firmware. To keep a unified approach, once the firmware has completed its power off sequence, disable IRQs for the while GPU at the kernel level instead. Signed-off-by: Alessio Belle --- drivers/gpu/drm/imagination/pvr_power.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imagination/pvr_power.c index f50cdea30680..3f22b07e3301 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -92,9 +92,9 @@ pvr_power_request_pwr_off(struct pvr_device *pvr_dev) static int pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspend) { - if (!hard_reset) { - int err; + int err; + if (!hard_reset) { cancel_delayed_work_sync(&pvr_dev->watchdog.work); err = pvr_power_request_idle(pvr_dev); @@ -107,33 +107,46 @@ pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspe } if (rpm_suspend) { - /* Wait for late processing of GPU or firmware IRQs in other cores */ - synchronize_irq(pvr_dev->irq); + /* This also waits for late processing of GPU or firmware IRQs in other cores */ + disable_irq(pvr_dev->irq); } - return pvr_fw_stop(pvr_dev); + err = pvr_fw_stop(pvr_dev); + if (err && rpm_suspend) + enable_irq(pvr_dev->irq); + + return err; } static int -pvr_power_fw_enable(struct pvr_device *pvr_dev) +pvr_power_fw_enable(struct pvr_device *pvr_dev, bool rpm_resume) { int err; + if (rpm_resume) + enable_irq(pvr_dev->irq); + err = pvr_fw_start(pvr_dev); if (err) - return err; + goto out; err = pvr_wait_for_fw_boot(pvr_dev); if (err) { drm_err(from_pvr_device(pvr_dev), "Firmware failed to boot\n"); pvr_fw_stop(pvr_dev); - return err; + goto out; } queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work, msecs_to_jiffies(WATCHDOG_TIME_MS)); return 0; + +out: + if (rpm_resume) + disable_irq(pvr_dev->irq); + + return err; } bool @@ -396,7 +409,7 @@ pvr_power_device_resume(struct device *dev) goto err_drm_dev_exit; if (pvr_dev->fw_dev.booted) { - err = pvr_power_fw_enable(pvr_dev); + err = pvr_power_fw_enable(pvr_dev, true); if (err) goto err_power_off; } @@ -546,7 +559,7 @@ pvr_power_reset(struct pvr_device *pvr_dev, bool hard_reset) pvr_fw_irq_clear(pvr_dev); - err = pvr_power_fw_enable(pvr_dev); + err = pvr_power_fw_enable(pvr_dev, false); } if (err && hard_reset) -- 2.43.0