From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 274D9FD2D74 for ; Tue, 10 Mar 2026 13:20:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D17010E271; Tue, 10 Mar 2026 13:20:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="StyWuhXC"; dkim-atps=neutral Received: from sea.source.kernel.org (sea.source.kernel.org [172.234.252.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6D60710E271; Tue, 10 Mar 2026 13:20:36 +0000 (UTC) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 10D1940823; Tue, 10 Mar 2026 13:20:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0192EC19423; Tue, 10 Mar 2026 13:20:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773148835; bh=Dygqb+VzJFlCPr/Paizij05sMxwUrE4iBosntsxs0tM=; h=From:Date:Subject:To:Cc:From; b=StyWuhXCzyJPk3LDKL7W5Aop9vEpK/sOED+tkAGXCKWDpnYRyPyZ8gepSfYCv8N9c P6DUnDMu08vaDQ+T9AVnyexvMQhfQKj8GjAxcI6VDVPwuCeQJ5zuh8NampsKPTcLFG dSh7TkeVr+YlAVtWT0xqQxQQEJoU1iNUm1sgTBDwSMmeH+8A5NyALV3JszXqyW4DEB AkeyQYy6B3GBZFb7KvZkZOZS9g4pdXoOhgbVdlWbX4yvYHaP5NfHDDazDWQrv1yItz Mr3NWwgBx5+bPitEtp7UnSTlR+dVkeRycGKOdwzm2kPNtAYeyc9/W8tMWPqNKbifoS aOOlcAEtN+uvA== From: Konrad Dybcio Date: Tue, 10 Mar 2026 14:20:25 +0100 Subject: [PATCH] drm/msm/mdss: Add a TODO for better managing the MDSS clock power state MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260310-topic-mdss_power_todo-v1-1-59457b8b7486@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/x3MSwqAMAwA0atI1hZaf6hXERFpU81CUxpRQby7x eVbzDwgGAkF+uyBiCcJ8Z5g8gzsOu8LKnLJUOii0aXR6uBAVm1OZAp8YZwOdqyq2XTW1742bQm pDRE93f93GN/3A767X6lnAAAA X-Change-ID: 20260310-topic-mdss_power_todo-4a19cf5f5183 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773148832; l=1793; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=FGbnaUib9uRu3abrN32AWgJZlFWuy/Q28ilmx5hne0s=; b=SsdDusLV3PkFtfEmX/JhXKfvIIQgT/GvlF9E1F2H4805D60ZW9D0hSaTq9sW0uMvx9wJcksqk BQ/ADkzlTQuAANHLdS8ZSE9n6WlFB4KbshpEtz2lAOWhIFmSPyAPrNY X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Konrad Dybcio There's a small window where the MDP clock could be set to a high rate (say, from the bootloader) without a corresponding RPM(H)PD vote to back it up. This is normally not an issue, but could be, if rmmod fails to shut down the display driver cleanly, and the module is inserted again, or when the providers' .sync_state has timed out. Mark a TODO to fix it one day. Linking the relevant discussion below. Link: https://lore.kernel.org/linux-arm-msm/d5c4eed5-bd87-4156-b178-2d78140ec8a9@oss.qualcomm.com/ Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 9047e8d9ee89..b783dfec83b8 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -262,6 +262,14 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) icc_set_bw(msm_mdss->reg_bus_path, 0, msm_mdss->reg_bus_bw); + /* + * TODO: + * Previous users (e.g. the bootloader) may have left this clock at a high rate, which + * would remain set, as prepare_enable() doesn't reprogram it. This theoretically poses a + * risk of brownout, but realistically this path is almost exclusively excercised after the + * correct OPP has been set in one of the MDPn or DPU drivers, or during initial probe, + * before the RPM(H)PD sync_state is done. + */ ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); --- base-commit: fc7b1a72c6cd5cbbd989c6c32a6486e3e4e3594d change-id: 20260310-topic-mdss_power_todo-4a19cf5f5183 Best regards, -- Konrad Dybcio