From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B40AF103E2EB for ; Wed, 11 Mar 2026 23:04:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0913810E404; Wed, 11 Mar 2026 23:04:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=collabora.com header.i=deborah.brouwer@collabora.com header.b="ZSklmOHg"; dkim-atps=neutral Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) by gabe.freedesktop.org (Postfix) with ESMTPS id AAC2D10E402 for ; Wed, 11 Mar 2026 23:04:27 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; t=1773270264; cv=none; d=zohomail.com; s=zohoarc; b=eRyUu54qCLa+h98tNXW7uJVgmnEYgqeNyrybQ/QcGukILM4Z70RzRbEijujuJYXODloSaZt4jjk4mjvljGzCneEyNlcxbsXkppyXDWHQCxTq9ZeDiYOXZwyFDyR2SCTl7gS9Q5an/HQq9gMeH8WDlWyWTJYM/h5C3cAl/R/2Jt4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773270264; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=wbj/vUuubjkTwZ1s+U/xf1asRmAUCKpgh4SoFzbZXOE=; b=AYLfJon5aIvAfklWUQABox9uT/v3dShVfMZ/c7rf3f4dxw6AXOWLEDKOYiOZ0VxwgAkLh9ax3VejjnH8QR2C5q4Hs75DwjFk99P8qk0EEe7Snhg7x7M61ngOT4WlYOKPcNdnz3PhGrCuqv4QBLMRIe45sTyGLr0jO+hGDpKPVok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=deborah.brouwer@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1773270264; s=zohomail; d=collabora.com; i=deborah.brouwer@collabora.com; h=From:From:Subject:Subject:Date:Date:Message-Id:Message-Id:MIME-Version:Content-Type:Content-Transfer-Encoding:To:To:Cc:Cc:Reply-To; bh=wbj/vUuubjkTwZ1s+U/xf1asRmAUCKpgh4SoFzbZXOE=; b=ZSklmOHgjQkkroIF8mshPIMd9jWgBET986yeSSc/HHkMQaatGSgWFTtgCniTPmxW ZpMunv2Zff7gDtA4ZmrC8zkJ2ZSzos16oCkunv3pT0S+mgbxSVlfQwbqnTW3kUomulQ AJnamjjTSicyxibBp3yX+0UqrB+dc3791enya+aE= Received: by mx.zohomail.com with SMTPS id 17732702616444.146161533229929; Wed, 11 Mar 2026 16:04:21 -0700 (PDT) From: Deborah Brouwer Subject: [PATCH v2 0/5] drm/tyr: Use register! macro Date: Wed, 11 Mar 2026 16:03:57 -0700 Message-Id: <20260311-b4-tyr-use-register-macro-v2-v2-0-b936d9eb8f51@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAN30sWkC/x3MMQ6DMAwAwK8gz1hKUlKVfgUxhOCmHoDKBlQU8 Xcixlsug5IwKbyrDEI7Ky9zgasriN8wJ0Iei8EZ9zQPa3FocD0ENyUUSqwrCU4hyoK7wzjGV2u 9N40PUIqf0If/d9/153kBwJT9/24AAAA= X-Change-ID: 20260311-b4-tyr-use-register-macro-v2-cdc89155045a To: dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org Cc: Danilo Krummrich , Alice Ryhl , Daniel Almeida , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Miguel Ojeda , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Steven Price , Boris Brezillon , Dirk Behme , Alexandre Courbot , Deborah Brouwer , Boqun Feng X-Mailer: b4 0.14.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This series changes the Tyr driver to use the kernel's register! macro for hardware register access, replacing manual bit manipulation and custom register structures with a more type-safe and maintainable approach. Signed-off-by: Deborah Brouwer --- This series depends on: [PATCH v8 00/10] rust: add `register!` macro https://lore.kernel.org/rust-for-linux/20260310-register-v8-0-424f80dd43bc@nvidia.com/ Changes in v2: - Rebase on v8 of register! macro series; - Add documentation; - Remove manual functions to get address bits; - Revise gpu_info() to use macro; - Revise l2_power_on() to use macro; - Set interconnect coherency protocol with macro; - Separate commits for each register page; - Replace HI/LO pairs with 64bit registers - Order registers by address; - Remove doorbell clear field from GPU_IRQ_CLEAR; - GPU command is redesigned to accommodate multiple layouts; - MMU register bits corrected; - Use UPPERCASE for register names; - Move the consts to impl block for registers; --- Daniel Almeida (1): drm/tyr: Use register! macro for GPU_CONTROL Deborah Brouwer (4): drm/tyr: Set interconnect coherency during probe drm/tyr: Use register! macro for JOB_CONTROL drm/tyr: Use register! macro for MMU_CONTROL drm/tyr: Remove custom register struct drivers/gpu/drm/tyr/driver.rs | 32 +- drivers/gpu/drm/tyr/gpu.rs | 213 +++++------- drivers/gpu/drm/tyr/regs.rs | 785 ++++++++++++++++++++++++++++++++++++------ 3 files changed, 792 insertions(+), 238 deletions(-) --- base-commit: 91c02cfa16427b078c8a74f2b96123b579fdb07f change-id: 20260311-b4-tyr-use-register-macro-v2-cdc89155045a Best regards, -- Deborah Brouwer