From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACD82103E2EF for ; Wed, 11 Mar 2026 23:04:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 070B210E40A; Wed, 11 Mar 2026 23:04:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=collabora.com header.i=deborah.brouwer@collabora.com header.b="Sm13O96B"; dkim-atps=neutral Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) by gabe.freedesktop.org (Postfix) with ESMTPS id CAD5A10E409 for ; Wed, 11 Mar 2026 23:04:32 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; t=1773270270; cv=none; d=zohomail.com; s=zohoarc; b=b9tNZqkXV2H3hS+EfXkqhAYLOf6Utbgr8TyuKRW6r79q9pyFx6wUbC74GlVb7OYnyTI2NXuFcxLNthySMSdaP3Ckzy85udJ8AVeEkjWWaEAUrMUuwyxkMvM8HjRhvYK/MAtA5IS/lJH6KK64tJ66fSZ2XQ2/S8zrkOj8Sf+VTUQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773270270; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=iTybMURHQ311bMbIiYhoFOdTrxlhhPYel+M+GNgLouo=; b=IGpNWAjzUnMRtjZnNS77L/pcsii7HecyvKy2IyjAAk0VgaRaswf5xLIPRe+JSmNVMbxud48jOWTWcn+1T0KWldYMCvYWGa8b42Cuf/1Yq0OevK/Av93fVCsYYxCNuvOSaV/rH/4OZtG4kBYwytMt8Xw8riPedKXzVRbVmgsojsg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=deborah.brouwer@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1773270270; s=zohomail; d=collabora.com; i=deborah.brouwer@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=iTybMURHQ311bMbIiYhoFOdTrxlhhPYel+M+GNgLouo=; b=Sm13O96BmHn6GR6kOrxoWRueNzKW2usX1rkVt+js03AFKu8XaSNzIqNGKMYRzYrn CUlL8wMZP0PuHN2PxyZ4M082ykJrOkT8MYkrJqLiqB8cWYfA+NUGqTu1+o1g8MU/rXX enHOZ0bvEtAjhRRZ8RUrCTGQMtELJak78og3r1d0= Received: by mx.zohomail.com with SMTPS id 1773270268071883.1934255356537; Wed, 11 Mar 2026 16:04:28 -0700 (PDT) From: Deborah Brouwer Date: Wed, 11 Mar 2026 16:04:02 -0700 Subject: [PATCH v2 5/5] drm/tyr: Remove custom register struct MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260311-b4-tyr-use-register-macro-v2-v2-5-b936d9eb8f51@collabora.com> References: <20260311-b4-tyr-use-register-macro-v2-v2-0-b936d9eb8f51@collabora.com> In-Reply-To: <20260311-b4-tyr-use-register-macro-v2-v2-0-b936d9eb8f51@collabora.com> To: dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org Cc: Danilo Krummrich , Alice Ryhl , Daniel Almeida , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Miguel Ojeda , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Steven Price , Boris Brezillon , Dirk Behme , Alexandre Courbot , Deborah Brouwer , Boqun Feng X-Mailer: b4 0.14.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Now that Tyr uses the register! macro, it no longer needs to define a custom register struct or read/write functions, so delete them. Co-developed-by: Daniel Almeida Signed-off-by: Daniel Almeida Signed-off-by: Deborah Brouwer --- drivers/gpu/drm/tyr/regs.rs | 33 --------------------------------- 1 file changed, 33 deletions(-) diff --git a/drivers/gpu/drm/tyr/regs.rs b/drivers/gpu/drm/tyr/regs.rs index 6c16a041ab3c36f8aaf785487ad61925be65a026..3fc5101c2dcd5d892abc726ea07d75d8f22b5d23 100644 --- a/drivers/gpu/drm/tyr/regs.rs +++ b/drivers/gpu/drm/tyr/regs.rs @@ -27,39 +27,6 @@ // does. #![allow(dead_code)] -use kernel::{ - device::{ - Bound, - Device, // - }, - devres::Devres, - io::Io, - prelude::*, // -}; - -use crate::driver::IoMem; - -/// Represents a register in the Register Set -/// -/// TODO: Replace this with the Nova `register!()` macro when it is available. -/// In particular, this will automatically give us 64bit register reads and -/// writes. -pub(crate) struct Register; - -impl Register { - #[inline] - pub(crate) fn read(&self, dev: &Device, iomem: &Devres) -> Result { - let value = (*iomem).access(dev)?.read32(OFFSET); - Ok(value) - } - - #[inline] - pub(crate) fn write(&self, dev: &Device, iomem: &Devres, value: u32) -> Result { - (*iomem).access(dev)?.write32(value, OFFSET); - Ok(()) - } -} - /// These registers correspond to the GPU_CONTROL register page. /// They are involved in GPU configuration and control. pub(super) mod gpu_control { -- 2.52.0