From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E713112588E for ; Wed, 11 Mar 2026 20:17:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A57D410E928; Wed, 11 Mar 2026 20:17:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.b="kMgiB8P0"; dkim=pass (2048-bit key; unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="FOTk6coQ"; dkim-atps=neutral Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB13910E927 for ; Wed, 11 Mar 2026 20:17:51 +0000 (UTC) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62BGDlvR294409 for ; Wed, 11 Mar 2026 20:17:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= WUfDsXE2bewsJbQrNcPdTtiQ5aMigLmKp8tPDJLp/a0=; b=kMgiB8P0H8w3+zT3 FcgU+Aq5DunS/yH6Yl/Hn5mt3MbzvC9njX2Xf4BTEM0IYc2fZ4A0plMQKX5/y4NU Ah2BwRpgWoXgFFiKmuqNpBKXmtamNMqBR99YhgLzS8TvvNi42qcQzz/+bmv2YuQw sqTMLqQ+E5wKrwhL0LK9A5TZ0u7IZPJc/3aF4ejtTXpZGV1vO+CYNFVZy7JGdwt4 2fqUtV82qd7H+UN6nuUV8OI/S46E/Zr5LfGJb6t5Xsg1gu1vSpkMx/eh+A/3QB1I TTMZ+aDBk5XtjiN1B5tcCfGp+bgTsnUeLSEpRE4ZkoO82bP4TPmr9hNQDZSn94Sf AW1RiQ== Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cu6bba4t5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 11 Mar 2026 20:17:51 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-8cb52a9c0eeso198075185a.2 for ; Wed, 11 Mar 2026 13:17:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773260270; x=1773865070; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WUfDsXE2bewsJbQrNcPdTtiQ5aMigLmKp8tPDJLp/a0=; b=FOTk6coQEYXdZv1VStTZIxdUg8Ujypbf05F/WK1WyElp2Z7nDMRuJ/o88Zd02dNYqV xfFmCOftOa4gaMgzmpnhf361cP5WUEcIWFbGutGXpmzpJI0aYxQhXgVdncQ9W3O+xmrr z1T1hEf0yY9up9/fV6erfhEo9UbFAr65/dtNRdYcGsvh+uE6yQymEpbTw2yiP46HeZKJ 0YORfQMR8nlmQ0DKjSNjygDzeXoSHaIu4vy32ZZK9Vgno9Z5Uw7bPHuzHfanWYqQSmT+ 1I39AVF7fE/IoJSU+ZngUSTbulCzSLvu+xwJTh+7zt5orKtOT0JxoTBOXv0D6BDZeG1Z HFPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773260270; x=1773865070; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=WUfDsXE2bewsJbQrNcPdTtiQ5aMigLmKp8tPDJLp/a0=; b=W/4dlEwmmJEEAZenrOq8hPr6dvJzd4Lx2VU3t8NRBtullyWcC8DVORrU2/SSF3wypK 002OLscN7QSGusNfcV6DtgO3TK3ecmXWhbW19Q31FsL/S32gtn4E6ChPbH3H5J/tUo49 yylIui+5AwuwdSYKEba7kczlSKXZJAFQYj3x5uL94hahreVpxKDZb4sCOAp/B8u175Q5 Q5EqXKdTtYT1SvDHcQqDDxcmTCUzyVbxdjV7CNgSFWQL7I1BG/9A3ajVDFlvYKllJEk6 RBB+DrZhlNwiOrWHdW30TOfVLW7Ocr7qH3DQcq6PqF0N3l9Fa+34FL4w46AG3cAKAMco 4CHA== X-Forwarded-Encrypted: i=1; AJvYcCXAMRyFwa3drAtogzc4iM1AhHPAeZi74fMy45l3+IRyYzR2/r0vuoqB89r63yvclPhtvSMcDroaNuI=@lists.freedesktop.org X-Gm-Message-State: AOJu0YwwTy7dx6jtLdD0nHwmTQlG5IGutX+v3FIRUHMpv8VibxX918Bb Kw+Vw9zFiiMTr7qtj0a+7pQXNJnHpMhsEgwk0j+vvmqZh8vd2zNLPQaVbgi3RrsfnspJk8a5rBA rMMNfSrMUJQ2BJqOFAG/KF/mDtv5v1oitVKOg1wOC7vCSAW2CCIDgLX/O1mayBgpILv+vI3Q= X-Gm-Gg: ATEYQzzH2VTQCIuj3JBTswXOO15AAkXtF+py94qQK4YQ78jdfzXde/+7evKOU6XmVrG s/vDwv9NpITtgCBKm4+/J3twDLLUWP8rGhF8WvtTRAsvTZuR5FDYqNCX4dIm0PBYKGXC402bVOH s5Bn5paP7FGEHTEbbMGZBY/DYqIaLBKt1UclMQnxb2WToyjE8WmmG38QidCQ/mth8AHIxz/qyE1 nggiwk2OYYRfsG9UTklJK/9ID5j1orCYGdylcptpEtJIrgmwgp8gtkoBPn8Oi4ff5odxm5ONR+G zJHVkLTfqO9Un1ceGb5QgSqWZmSaLIWShr8K5sGffzSFboFe51vZzTV4Agdd1fN9SLHjyb7OF5n fEp7SNOng8Ijq5RhHoKcxJINKOzhwWWcd+BjvnHEmxbX0 X-Received: by 2002:a05:620a:708a:b0:8cb:4059:a909 with SMTP id af79cd13be357-8cda1956ac0mr553433185a.21.1773260270148; Wed, 11 Mar 2026 13:17:50 -0700 (PDT) X-Received: by 2002:a05:620a:708a:b0:8cb:4059:a909 with SMTP id af79cd13be357-8cda1956ac0mr553428485a.21.1773260269682; Wed, 11 Mar 2026 13:17:49 -0700 (PDT) Received: from [127.0.1.1] ([178.197.219.94]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4854b65fd3dsm79257255e9.10.2026.03.11.13.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 13:17:48 -0700 (PDT) From: Krzysztof Kozlowski Date: Wed, 11 Mar 2026 21:17:31 +0100 Subject: [PATCH 7/7] drm/msm/hdmi_hdcp: Simplify register bit updates MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260311-drm-msm-hdmi-cleanup-v1-7-c5535245f6de@oss.qualcomm.com> References: <20260311-drm-msm-hdmi-cleanup-v1-0-c5535245f6de@oss.qualcomm.com> In-Reply-To: <20260311-drm-msm-hdmi-cleanup-v1-0-c5535245f6de@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=9385; i=krzysztof.kozlowski@oss.qualcomm.com; h=from:subject:message-id; bh=8XMa4wsTUcexijaN95Xa/+lE5OvRgvIaBdz6gmBRNU8=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBpsc3cfvxWGj/HrNqippRl5yeLDVnfLLiTatfgb vOaaMf4BPGJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCabHN3AAKCRDBN2bmhouD 1447D/0QPvgUPTbzaC5cY2j7uyYgBrjkju5R1+H21BG9UvvJd+Wxz+McNqCfV34gBK1EPc7bfg7 bD0TUjKJByBioIN+3gL2RZiJJxucvEqsFWmhWxTuOZoFOndaUuymfzBCJMD6EyBPIwk+0Y3VLPq xaxMRrylzi0WnRCxTb6DQqprOOyYBaW/N9C4LFDnvQMbFyTlLLfsiRkVn1WLBkRL1k9ABay7Hoh OuoZRTjgAJjnwmUDR19X/XpiqLYW60aNRv9aNUQJ+12pDskGNQRIAH/TPsZaZ3PSkn0CplVjNOW ESxaZSXWFs5MhcjUpxE4Ot3jS1IgUNz48eclsE96oOucjC+g1CEoX2CeCIucAnEzqYJRbCmuHLH eFLzbiuyUZWedLS4HHY+Hlw/laVRyRl7+wtsAUMIw2nGTfs/wOctan2i/swBiXVyYrVnkSkK5mO YuuFYK4sy1i+2WdhyDbmYkwM9A7VPDXEJaVM+2L6aAEGg5hbZzRwOSrB1r1uPqZE/vLtegZGqCs 6xrcmPEaEWXLQw66S/iNiwbwOar0l3ZgWkiEu99PmHy5AoozRAfuAaZ6UvCAukuANQiq8Ak1/1Q DD+MquVqa7BMAx6JuvwQMY55m3k/DFNbh8jesZfro1no9WwgJBbA6kulK8c9DV5indwq0TQJcTU lL0VK0Gn4XITvMw== X-Developer-Key: i=krzysztof.kozlowski@oss.qualcomm.com; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B X-Proofpoint-ORIG-GUID: BXQeP8Z89Bz-a-bgDBxw73SBXIQOaRtp X-Proofpoint-GUID: BXQeP8Z89Bz-a-bgDBxw73SBXIQOaRtp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDE3MiBTYWx0ZWRfX8iMw2//H2WcC GPO9EymwDzk/Z7fIQfgFh+/zyg1HVUB6lJebqi0BSpZYDedyGqrQscAfHGq3r4plLwuKpR273Yj NtuccxvXL40r+XtMTENGH7ssjGSokF0/CtlSZRoHdQ+5kGX/QTWBCss7EjZAy0aC7fIbGTog5ww SFGCrhyiT+TnVuxuT9/6UiQ7FPsbLJBrlDcpHKLOOlQI8qSMHzHW53klmiUpOeHvN78QqegQyIM OrMO+MMazPkZS8HNeIJ7/P8rflmYC1w6wFWeRDCtlXA1VJXmIpCTLtGZqROEpiyXvSHLO1bJFMm Ntx3h10nxr55fc5vxcl8cIhM5kSbkyuIqBnpFzLVA+Mw/XMsDu5nIms1OF0GozvNcxKJE8lpd/h PWWo0KE2L074TA8+25KSzIUH8rC3+m6RyPEk1BVPFHj9wgqSAUytbUf7IsuhZZZ/ORKXmwKxIIB Sa4LsfM9TZaDvDqTnCQ== X-Authority-Analysis: v=2.4 cv=CKwnnBrD c=1 sm=1 tr=0 ts=69b1cdef cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=gOEeR9iKwsj33Yj5oN/cWg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=kVIxuixzSQivcz-PG0cA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-11_02,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 adultscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110172 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Simplify reister updates (read, apply mask, write) with a wrapper to make code more obvious and avoid possible errors of reading and writing to different registers. Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c | 85 ++++++++++++------------------------ 1 file changed, 28 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c b/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c index 8fb5497aac9f..7862bd67d154 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c @@ -306,9 +306,9 @@ static int msm_reset_hdcp_ddc_failures(struct hdmi_hdcp_ctrl *hdcp_ctrl) HDMI_HDCP_DDC_CTRL_0_DISABLE); /* ACK the Failure to Clear it */ - reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_CTRL_1); - reg_val |= HDMI_HDCP_DDC_CTRL_1_FAILED_ACK; - hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_1, reg_val); + hdmi_update_bits(hdmi, REG_HDMI_HDCP_DDC_CTRL_1, + HDMI_HDCP_DDC_CTRL_1_FAILED_ACK, + HDMI_HDCP_DDC_CTRL_1_FAILED_ACK); /* Check if the FAILURE got Cleared */ reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); @@ -324,28 +324,22 @@ static int msm_reset_hdcp_ddc_failures(struct hdmi_hdcp_ctrl *hdcp_ctrl) DBG("Before: HDMI_DDC_SW_STATUS=0x%08x", hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS)); /* Reset HDMI DDC software status */ - reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); - reg_val |= HDMI_DDC_CTRL_SW_STATUS_RESET; - hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); + hdmi_update_bits(hdmi, REG_HDMI_DDC_CTRL, HDMI_DDC_CTRL_SW_STATUS_RESET, + HDMI_DDC_CTRL_SW_STATUS_RESET); rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); - reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); - reg_val &= ~HDMI_DDC_CTRL_SW_STATUS_RESET; - hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); + hdmi_clear_bits(hdmi, REG_HDMI_DDC_CTRL, HDMI_DDC_CTRL_SW_STATUS_RESET); /* Reset HDMI DDC Controller */ - reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); - reg_val |= HDMI_DDC_CTRL_SOFT_RESET; - hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); + hdmi_update_bits(hdmi, REG_HDMI_DDC_CTRL, HDMI_DDC_CTRL_SOFT_RESET, + HDMI_DDC_CTRL_SOFT_RESET); /* If previous msleep is aborted, skip this msleep */ if (!rc) rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); - reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); - reg_val &= ~HDMI_DDC_CTRL_SOFT_RESET; - hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); + hdmi_clear_bits(hdmi, REG_HDMI_DDC_CTRL, HDMI_DDC_CTRL_SOFT_RESET); DBG("After: HDMI_DDC_SW_STATUS=0x%08x", hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS)); } @@ -399,7 +393,6 @@ static void msm_hdmi_hdcp_reauth_work(struct work_struct *work) struct hdmi_hdcp_ctrl, hdcp_reauth_work); struct hdmi *hdmi = hdcp_ctrl->hdmi; unsigned long flags; - u32 reg_val; DBG("HDCP REAUTH WORK"); /* @@ -409,9 +402,7 @@ static void msm_hdmi_hdcp_reauth_work(struct work_struct *work) * AN1_READY bits in HDMI_HDCP_LINK0_STATUS register */ spin_lock_irqsave(&hdmi->reg_lock, flags); - reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); - reg_val &= ~HDMI_HPD_CTRL_ENABLE; - hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); + hdmi_clear_bits(hdmi, REG_HDMI_HPD_CTRL, HDMI_HPD_CTRL_ENABLE); /* Disable HDCP interrupts */ hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, 0); @@ -431,9 +422,8 @@ static void msm_hdmi_hdcp_reauth_work(struct work_struct *work) /* Enable HPD circuitry */ spin_lock_irqsave(&hdmi->reg_lock, flags); - reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); - reg_val |= HDMI_HPD_CTRL_ENABLE; - hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); + hdmi_update_bits(hdmi, REG_HDMI_HPD_CTRL, HDMI_HPD_CTRL_ENABLE, + HDMI_HPD_CTRL_ENABLE); spin_unlock_irqrestore(&hdmi->reg_lock, flags); /* @@ -456,7 +446,6 @@ static int msm_hdmi_hdcp_auth_prepare(struct hdmi_hdcp_ctrl *hdcp_ctrl) { struct hdmi *hdmi = hdcp_ctrl->hdmi; u32 link0_status; - u32 reg_val; unsigned long flags; int rc; @@ -472,14 +461,11 @@ static int msm_hdmi_hdcp_auth_prepare(struct hdmi_hdcp_ctrl *hdcp_ctrl) spin_lock_irqsave(&hdmi->reg_lock, flags); /* disable HDMI Encrypt */ - reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); - reg_val &= ~HDMI_CTRL_ENCRYPTED; - hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); + hdmi_clear_bits(hdmi, REG_HDMI_CTRL, HDMI_CTRL_ENCRYPTED); /* Enabling Software DDC */ - reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION); - reg_val &= ~HDMI_DDC_ARBITRATION_HW_ARBITRATION; - hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val); + hdmi_clear_bits(hdmi, REG_HDMI_DDC_ARBITRATION, + HDMI_DDC_ARBITRATION_HW_ARBITRATION); spin_unlock_irqrestore(&hdmi->reg_lock, flags); /* @@ -498,9 +484,8 @@ static int msm_hdmi_hdcp_auth_prepare(struct hdmi_hdcp_ctrl *hdcp_ctrl) hdmi_write(hdmi, REG_HDMI_HDCP_ENTROPY_CTRL1, 0xF00DFACE); /* Disable the RngCipher state */ - reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DEBUG_CTRL); - reg_val &= ~HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER; - hdmi_write(hdmi, REG_HDMI_HDCP_DEBUG_CTRL, reg_val); + hdmi_clear_bits(hdmi, REG_HDMI_HDCP_DEBUG_CTRL, + HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER); DBG("HDCP_DEBUG_CTRL=0x%08x", hdmi_read(hdmi, REG_HDMI_HDCP_DEBUG_CTRL)); @@ -537,15 +522,12 @@ static int msm_hdmi_hdcp_auth_prepare(struct hdmi_hdcp_ctrl *hdcp_ctrl) static void msm_hdmi_hdcp_auth_fail(struct hdmi_hdcp_ctrl *hdcp_ctrl) { struct hdmi *hdmi = hdcp_ctrl->hdmi; - u32 reg_val; unsigned long flags; DBG("hdcp auth failed, queue reauth work"); /* clear HDMI Encrypt */ spin_lock_irqsave(&hdmi->reg_lock, flags); - reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); - reg_val &= ~HDMI_CTRL_ENCRYPTED; - hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); + hdmi_clear_bits(hdmi, REG_HDMI_CTRL, HDMI_CTRL_ENCRYPTED); spin_unlock_irqrestore(&hdmi->reg_lock, flags); hdcp_ctrl->hdcp_state = HDCP_STATE_AUTH_FAILED; @@ -555,7 +537,6 @@ static void msm_hdmi_hdcp_auth_fail(struct hdmi_hdcp_ctrl *hdcp_ctrl) static void msm_hdmi_hdcp_auth_done(struct hdmi_hdcp_ctrl *hdcp_ctrl) { struct hdmi *hdmi = hdcp_ctrl->hdmi; - u32 reg_val; unsigned long flags; /* @@ -563,16 +544,15 @@ static void msm_hdmi_hdcp_auth_done(struct hdmi_hdcp_ctrl *hdcp_ctrl) * there is no Arbitration between software and hardware for DDC */ spin_lock_irqsave(&hdmi->reg_lock, flags); - reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION); - reg_val |= HDMI_DDC_ARBITRATION_HW_ARBITRATION; - hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val); + hdmi_update_bits(hdmi, REG_HDMI_DDC_ARBITRATION, + HDMI_DDC_ARBITRATION_HW_ARBITRATION, + HDMI_DDC_ARBITRATION_HW_ARBITRATION); spin_unlock_irqrestore(&hdmi->reg_lock, flags); /* enable HDMI Encrypt */ spin_lock_irqsave(&hdmi->reg_lock, flags); - reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); - reg_val |= HDMI_CTRL_ENCRYPTED; - hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); + hdmi_update_bits(hdmi, REG_HDMI_CTRL, HDMI_CTRL_ENCRYPTED, + HDMI_CTRL_ENCRYPTED); spin_unlock_irqrestore(&hdmi->reg_lock, flags); hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATED; @@ -1304,7 +1284,6 @@ static void msm_hdmi_hdcp_auth_work(struct work_struct *work) void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) { struct hdmi *hdmi = hdcp_ctrl->hdmi; - u32 reg_val; unsigned long flags; if ((HDCP_STATE_INACTIVE != hdcp_ctrl->hdcp_state) || @@ -1315,9 +1294,7 @@ void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) /* clear HDMI Encrypt */ spin_lock_irqsave(&hdmi->reg_lock, flags); - reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); - reg_val &= ~HDMI_CTRL_ENCRYPTED; - hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); + hdmi_clear_bits(hdmi, REG_HDMI_CTRL, HDMI_CTRL_ENCRYPTED); spin_unlock_irqrestore(&hdmi->reg_lock, flags); hdcp_ctrl->auth_event = 0; @@ -1330,7 +1307,6 @@ void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) { struct hdmi *hdmi = hdcp_ctrl->hdmi; unsigned long flags; - u32 reg_val; if ((HDCP_STATE_INACTIVE == hdcp_ctrl->hdcp_state) || (HDCP_STATE_NO_AKSV == hdcp_ctrl->hdcp_state)) { @@ -1345,9 +1321,7 @@ void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) * AN1_READY bits in HDMI_HDCP_LINK0_STATUS register */ spin_lock_irqsave(&hdmi->reg_lock, flags); - reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); - reg_val &= ~HDMI_HPD_CTRL_ENABLE; - hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); + hdmi_clear_bits(hdmi, REG_HDMI_HPD_CTRL, HDMI_HPD_CTRL_ENABLE); /* * Disable HDCP interrupts. @@ -1375,14 +1349,11 @@ void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, 0); spin_lock_irqsave(&hdmi->reg_lock, flags); - reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); - reg_val &= ~HDMI_CTRL_ENCRYPTED; - hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); + hdmi_clear_bits(hdmi, REG_HDMI_CTRL, HDMI_CTRL_ENCRYPTED); /* Enable HPD circuitry */ - reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); - reg_val |= HDMI_HPD_CTRL_ENABLE; - hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); + hdmi_update_bits(hdmi, REG_HDMI_HPD_CTRL, HDMI_HPD_CTRL_ENABLE, + HDMI_HPD_CTRL_ENABLE); spin_unlock_irqrestore(&hdmi->reg_lock, flags); hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE; -- 2.51.0