From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C603FD88EC for ; Wed, 11 Mar 2026 03:23:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B6B9610E7A2; Wed, 11 Mar 2026 03:23:23 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.b="mBqQFKbb"; dkim=pass (2048-bit key; unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="TOVFdsGq"; dkim-atps=neutral Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id EE07010E7A2 for ; Wed, 11 Mar 2026 03:23:21 +0000 (UTC) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62AIpeqs303881 for ; Wed, 11 Mar 2026 03:23:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= KDZZPG9DkNIoQAYC/ZQxpoKTbgw+/Pi/qUEgyBqUeUo=; b=mBqQFKbbO/V+Rc5G cz+jOpsOD1eQO79WD2MsOy7K3yJLqyYA8w/F2uzgvSdhBUtpxUHOHfeojxEujTr3 layt1dO05KYP5II5K6cZBXzD/y8yytThBo5I7CbHsYZdFaAyAL8I6vCi8rCjqo7F IvcuawqsFerOgv9H+kDf7Xt4R61lIcLlcuaM7M20c08Jx9J/puQ8fNFfaZICGisa g1RpAYHP4XuxBUFFNGI1Y+1t4UuXGTMce+GO/mMc/M5VMPf51mx+ofIgg/Q9gFJn wqWSp+67rb9dRUVkuOY1lzIUG3Y0OL4s9EEYpaDVB8grNY9AmDT/bSY+WwMnvFFN rds5IA== Received: from mail-vk1-f199.google.com (mail-vk1-f199.google.com [209.85.221.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cthjf3ekd-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 11 Mar 2026 03:23:21 +0000 (GMT) Received: by mail-vk1-f199.google.com with SMTP id 71dfb90a1353d-56b07903a75so8388067e0c.2 for ; Tue, 10 Mar 2026 20:23:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773199400; x=1773804200; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KDZZPG9DkNIoQAYC/ZQxpoKTbgw+/Pi/qUEgyBqUeUo=; b=TOVFdsGqku/81F7LyqB6ZwsLCENhRqHZWYzwBcC4VcdyA+9Bru9o96VlLz6y/S333s L4yAD8Ew14nGORqPLMZCrfWmkrYYrhHgag/W3b7xMbJmANaem7RNCo3pv17ub7GgQcf7 1TZTJAEhztVqc5ytd9T29DzVxWgRRrasF8Xpm9B1yJOCnH5k81tzmTJkObWKEIP7CaIf nqwzYcf/zo75tLE/XlI16bt55Auj6YaOte6ki0sPBCOEVdITLCxhVn21yjTEocwneY0R 0a6JW4gg3tIVwyjKorN4l2ashp+Hwd76ZsPMwIhKelPAogoCk30cY8k6w89dvkEn4B/V y46A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773199400; x=1773804200; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=KDZZPG9DkNIoQAYC/ZQxpoKTbgw+/Pi/qUEgyBqUeUo=; b=izhDJs85MO8S/+spsOLCcApdZIRREukb5zTG8vTp/RWeemXpYcjQDmTCCTbHms2Kaj 04UzmPEJizk1P4y3poTvgmmeQs8KM+6CRbh8dUHn256ybkKRh2EV5VIfwfIkbYuxz0UU ocU2RPL30UEI4dlPzMshnZkcaIe/mrnrrJG7MHhCLWyq0qtK2XTcbGDckBICMNrOyJrq jR+B9eHMJztjI3uW7wwBlTL6IB497HWoDjOsAwEwMvjeEvYxxPyYjJJ+vITWJIhNt1co ObyPzQM5I1I9VheJ6K8PKRcp6i/d04H6tcNnmktc5he6pKMTGKT6E0fp0jhE49ex4aEL +WPQ== X-Forwarded-Encrypted: i=1; AJvYcCVcQ33c6D2Sg0VaXDkY+Ci3O+ItMzJsaplvGl+2p1MK626IDaLkeGRGpVrzA7k7SumreZkNpMSjNbo=@lists.freedesktop.org X-Gm-Message-State: AOJu0YyrL83PTsfmMQiucZUfy6IXiKe35mtrmvX6yeIpnW45Fp2tdm4/ kONORm22bPNfbjZuogK8Fmp+U7oyeuB0v+TrVxd+t3dsQOJg3CO4QVxAdR4P0YEld+OUOdMy9SM 0DCV5LYnsHfshhqSXAG0PVMNi66BzbwLxDw1ZlKHoIcGm83rJiADDEO3P3fvPp1MQsdElhne8iO P9OJw= X-Gm-Gg: ATEYQzxHFeJQ/t6BNycrqoMlhzxyTq5ZmaV/tAQO4cIBxgJdYQMVvIS99LOmdAB8ie9 35cxLcFwnjGbVJCwo5IEf38p0AwD3zpUp8cg0ehIaja1bSlxortYLHQjwxDEJe7x6v0ohOTbMB6 bKwymBhUg0IAVr7M20LsWQHz7zwLExnMFKzqx3Kr08c7NpWh9gbU5tfUr1qu6MCFWmj1swp+r1H yXSDWk6s4h94QmB8jOcAw3gEidNq4erZzO2u5fpsl3CsuKFiDQW5NDljA2DXXrT78rwOj45AhoN FdustuqtIRej9qcy95pJabqYOB6Zy17AK8Mf8VK0t/YFd+W0GyfgBWXOIFPeNRs62OG3TGZc2sT Ww4eeMLAova8o+alAtgfWjaPexLU/3kmE1t3VmUwG9yZuprEPhpjw/BP/R0f/D0/i0+LFa3P3Vw +Tb4pRRiY2gA0dJcKeib3sKZi7wET25NxkGz4= X-Received: by 2002:a05:6122:90b:b0:56a:fc35:9664 with SMTP id 71dfb90a1353d-56b47438bcfmr367669e0c.3.1773199400226; Tue, 10 Mar 2026 20:23:20 -0700 (PDT) X-Received: by 2002:a05:6122:90b:b0:56a:fc35:9664 with SMTP id 71dfb90a1353d-56b47438bcfmr367657e0c.3.1773199399783; Tue, 10 Mar 2026 20:23:19 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67e5ed41sm1422721fa.25.2026.03.10.20.23.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 20:23:17 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 11 Mar 2026 05:22:55 +0200 Subject: [PATCH v2 01/25] drm/msm/mdss: correct UBWC programming sequences MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260311-ubwc-rework-v2-1-69f718f2a1c9@oss.qualcomm.com> References: <20260311-ubwc-rework-v2-0-69f718f2a1c9@oss.qualcomm.com> In-Reply-To: <20260311-ubwc-rework-v2-0-69f718f2a1c9@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6916; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=uSnw+FGxAf1+lIyAZwtg2QGOswUDFmlVWOT07uiqNc4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpsOAd1kg8HBo502twDi3RMzA/fa7vBmR7TiWDW tdDAL2OdBWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCabDgHQAKCRCLPIo+Aiko 1RfVB/wKZ1nWG1/vnjr7LfDjt7Y4o1OX2kv+6lepua9Tl2OeAtNUrdsR24baxlkBg1HBphtGhgl AZbi9JTmm1fmXcNXB6GJpqPY4anViI4CKqDfXujBKKoaqf/iFHrWWXJcsDZ7TRDBdsDdiBwibSQ f12jxT3pmItf60YWGOUU3keC3V2iPl2R3sumef0nCyMHQYjtPpNxRZ22GxuRtRnZ7wBjz0laAqD sjkgjumjo8Hw4BrDIQqRoCHz28u/WFUpRnx6ZULychiDnamOxLpZ+ZcF5Ybc7w4VtN5aa9qL1x8 y2Q7++zY1H+5ivL+SOrG3t8HRg0bFRJR6V2EaSHqreIxFwpV X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: 94hZwDpO7D80I7j2wtblcx509dtE-aPW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDAyNiBTYWx0ZWRfX74MZ1ByvDXPH NEkmrHkdvflWdL4omGbwvpmqq0K/Wn+EmRiYpECisMH9rMcH5wTgoc1OnpnGKyZB53blgtBy/Mx XBSIVNwHYHz5tu0nKRgs0wCN3wO0BEsZe6WE3hrWuQRZophtzfJN/lOqmm7n8QZ3ZWn+W1UiwJn nKwasDCoGO5n3guoTPYg5JUU7pSmxIAQMFqeJJP2C/oBBi8+SkHIvDOzgX4+jabP9PnQoHdMded joIBBsbccyNn4gFVo/y/n/8JE3M3TRQ+s3D8JAUjclL5bScklxTWXfvQ7nWdIORw6RiEXMm5Wx6 QxiCu93VLPw/Wi5ijY9f0JmaaPn3Qv9ckGL38OAAFl3fQaliGk8rk3BDI66G3J8GVw+GcYNtfom DgbU9H6Y+VgirxZK9jaHhcGQqCTafv7W4I5cegXDhO1XnYsuQ252wB6clVO0nwsDhzi4fOKsuCG HgWstzi2ALklwPgtfUQ== X-Authority-Analysis: v=2.4 cv=A71h/qWG c=1 sm=1 tr=0 ts=69b0e029 cx=c_pps a=+D9SDfe9YZWTjADjLiQY5g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=hQCg4X1xv2bm5S_WMKMA:9 a=QEXdDO2ut3YA:10 a=vmgOmaN-Xu0dpDh8OwbV:22 X-Proofpoint-ORIG-GUID: 94hZwDpO7D80I7j2wtblcx509dtE-aPW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_05,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 clxscore=1015 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110026 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The UBWC registers in the MDSS region are not dependent on the UBWC version (it is an invalid assumption we inherited from the vendor SDE driver). Instead they are dependent only on the MDSS core revision. Rework UBWC programming to follow MDSS revision and to use required (aka encoder) UBWC version instead of the ubwc_dec_version. Fixes: d68db6069a8e ("drm/msm/mdss: convert UBWC setup to use match data") Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 120 ++++++++++++++++------------------------- 1 file changed, 45 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 9047e8d9ee89..d8b0288f0040 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -166,27 +166,27 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) return 0; } -static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) +static void msm_mdss_4x_setup_ubwc(struct msm_mdss *msm_mdss) { const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; - u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); - if (data->ubwc_bank_spread) - value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; - if (data->ubwc_enc_version == UBWC_1_0) value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN(1); writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); } -static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) +static void msm_mdss_5x_setup_ubwc(struct msm_mdss *msm_mdss) { const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; - u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | + u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); + if (data->ubwc_bank_spread) + value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; + if (data->macrotile_mode) value |= MDSS_UBWC_STATIC_MACROTILE_MODE; @@ -199,11 +199,12 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); } -static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) +static void msm_mdss_6x_setup_ubwc(struct msm_mdss *msm_mdss) { const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); + u32 ver, prediction_mode; if (data->ubwc_bank_spread) value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; @@ -211,45 +212,42 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) if (data->macrotile_mode) value |= MDSS_UBWC_STATIC_MACROTILE_MODE; - writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); - - if (data->ubwc_enc_version == UBWC_3_0) { - writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); - writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); - } else { - if (data->ubwc_dec_version == UBWC_4_3) - writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); - else - writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); - writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); - } -} - -static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss) -{ - const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; - u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); - - if (data->ubwc_bank_spread) - value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; - - if (data->macrotile_mode) - value |= MDSS_UBWC_STATIC_MACROTILE_MODE; + if (data->ubwc_enc_version == UBWC_1_0) + value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN(1); writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); - if (data->ubwc_dec_version == UBWC_6_0) - writel_relaxed(5, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + if (data->ubwc_enc_version < UBWC_4_0) + prediction_mode = 0; else - writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); - - writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); + prediction_mode = 1; + + if (data->ubwc_enc_version >= UBWC_6_0) + ver = 5; + else if (data->ubwc_enc_version >= UBWC_5_0) + ver = 4; + else if (data->ubwc_enc_version >= UBWC_4_3) + ver = 3; + else if (data->ubwc_enc_version >= UBWC_4_0) + ver = 2; + else if (data->ubwc_enc_version >= UBWC_3_0) + ver = 1; + else /* UBWC 1.0 and 2.0 */ + ver = 0; + + writel_relaxed(ver, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + writel_relaxed(prediction_mode, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); } +#define MDSS_HW_VER(major, minor, step) \ + ((((major) & 0xf) << 28) | \ + (((minor) & 0xfff) << 16) | \ + ((step) & 0xffff)) + static int msm_mdss_enable(struct msm_mdss *msm_mdss) { int ret, i; + u32 hw_rev; /* * Several components have AXI clocks that can only be turned on if @@ -275,43 +273,15 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data) return 0; - /* - * ubwc config is part of the "mdss" region which is not accessible - * from the rest of the driver. hardcode known configurations here - * - * Decoder version can be read from the UBWC_DEC_HW_VERSION reg, - * UBWC_n and the rest of params comes from hw data. - */ - switch (msm_mdss->mdss_data->ubwc_dec_version) { - case 0: /* no UBWC */ - case UBWC_1_0: - /* do nothing */ - break; - case UBWC_2_0: - msm_mdss_setup_ubwc_dec_20(msm_mdss); - break; - case UBWC_3_0: - msm_mdss_setup_ubwc_dec_30(msm_mdss); - break; - case UBWC_4_0: - case UBWC_4_3: - msm_mdss_setup_ubwc_dec_40(msm_mdss); - break; - case UBWC_5_0: - msm_mdss_setup_ubwc_dec_50(msm_mdss); - break; - case UBWC_6_0: - msm_mdss_setup_ubwc_dec_50(msm_mdss); - break; - default: - dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", - msm_mdss->mdss_data->ubwc_dec_version); - dev_err(msm_mdss->dev, "HW_REV: 0x%x\n", - readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION)); - dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", - readl_relaxed(msm_mdss->mmio + REG_MDSS_UBWC_DEC_HW_VERSION)); - break; - } + hw_rev = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION); + + if (hw_rev >= MDSS_HW_VER(6, 0, 0)) + msm_mdss_6x_setup_ubwc(msm_mdss); + else if (hw_rev >= MDSS_HW_VER(5, 0, 0)) + msm_mdss_5x_setup_ubwc(msm_mdss); + else if (hw_rev >= MDSS_HW_VER(4, 0, 0)) + msm_mdss_4x_setup_ubwc(msm_mdss); + /* else UBWC 1.0 or none, no params to program */ return ret; } -- 2.47.3