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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67e5ed41sm1422721fa.25.2026.03.10.20.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 20:24:09 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 11 Mar 2026 05:23:15 +0200 Subject: [PATCH v2 21/25] soc: qcom: ubwc: drop ubwc_bank_spread MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260311-ubwc-rework-v2-21-69f718f2a1c9@oss.qualcomm.com> References: <20260311-ubwc-rework-v2-0-69f718f2a1c9@oss.qualcomm.com> In-Reply-To: <20260311-ubwc-rework-v2-0-69f718f2a1c9@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5290; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=+PboiHqalsz8Ki46I7DJHtRHTDwCOdkyCS8EhQsYshk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpsOAgr3F6Gn9p7+6+pWADTaYvdyN4nA918ZGU9 Xzl+X9VnFqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCabDgIAAKCRCLPIo+Aiko 1bO2CACq5quSnYP25Dnu/CHxK6BZOMxWDtmUMTmVWccG5Ip8pTlx+oNYBiCiOu9sm2fxx1Sf+iB MzyFyNIPUQIQHcHFU1aQ4TW0B71uSdif+O+rR8irJcMSksbb/OhgSx2F4vcWhOACbLXM0EqNjTM WrWZxybUcANffXuLdCqcggfV3zF88WNVJi3wcr0xGQtpv6XzaVi6180l6ff4Hd98TZVrwCufx4X XdehaTuwx39AuHvFDgau6DYeP32/M2UtQM9KDRLoQIp6z5k90/TNai/s3km0YTWEoERbHEa+bo8 bJBmJ+1XIeGIPoSLVoPipMFxAA/Qp9kyZpXVLYCfmbRkyjGU X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDAyNiBTYWx0ZWRfX9U43NRBjs3ZC lhsyEqG5oOjocDLoXjHulFPTaVHNIZ84eKYifQFX+31kG6GhffWMPayY04Fb1c1ne9fizMSktjF np+MXq1Wi6B2wbwnt0MtaQ1NukjT13Hjki/sjKdaeNNY1/4GqeN3DDJf6Voahul3pyChlr7V02O GT1orWnv04VK+2GdzoOuFS9pTMb2SHT0x4PVpjB1D9T2n1wkFMqGpiiymA5I69uR2kVEY/KnyOT /DkrDs5l+Ua5wW3+v/uAGs6Mvv92iHtoUTHrhODOTqkPePC8kLQkEMrAICLO0Nh1mf6lt5T4dPZ vDB0e4SYpryLaMDKoMoeV3RFmliiuwRvplqqBRZQ1D4HtuB2+i93Yjctj1QgFjWMNvUldMaYQJT qVS9LIn+wK3BQWAHYeX57kwI9qhBcmBD02prXNTHymKmzJomuoIgBG0hXZSggWueIQ/mIE87iWz pD95Igy1kDSXN5n1lUA== X-Proofpoint-GUID: n7zGDG6j-Hy1BlFoaDOhGUGIKuOoKVuq X-Authority-Analysis: v=2.4 cv=S5vUAYsP c=1 sm=1 tr=0 ts=69b0e05c cx=c_pps a=1Os3MKEOqt8YzSjcPV0cFA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=j0qWcOM9GDCbVNQ44DEA:9 a=QEXdDO2ut3YA:10 a=hhpmQAJR8DioWGSBphRh:22 X-Proofpoint-ORIG-GUID: n7zGDG6j-Hy1BlFoaDOhGUGIKuOoKVuq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_05,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 malwarescore=0 adultscore=0 bulkscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110026 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" According to the documentation, UBWC bank spreading should be enabled for all targets. It's just not all targets have separate bit to control it. Drop the bit from the database and make the helper always return true. If we need to change it later, the helper can be adjusted according to the programming guides. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/ubwc_config.c | 13 ------------- include/linux/soc/qcom/ubwc.h | 3 +-- 2 files changed, 1 insertion(+), 15 deletions(-) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index c5c7fcb4d013..070bf97e134e 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -20,7 +20,6 @@ static const struct qcom_ubwc_cfg_data kaanapali_data = { .ubwc_enc_version = UBWC_6_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 16, .macrotile_mode = true, }; @@ -49,7 +48,6 @@ static const struct qcom_ubwc_cfg_data qcm2290_data = { static const struct qcom_ubwc_cfg_data sa8775p_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 13, .macrotile_mode = true, }; @@ -58,7 +56,6 @@ static const struct qcom_ubwc_cfg_data sar2130p_data = { .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 13, .macrotile_mode = true, }; @@ -67,7 +64,6 @@ static const struct qcom_ubwc_cfg_data sc7180_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 14, }; @@ -75,7 +71,6 @@ static const struct qcom_ubwc_cfg_data sc7280_data = { .ubwc_enc_version = UBWC_3_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 14, .macrotile_mode = true, }; @@ -92,7 +87,6 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 16, .macrotile_mode = true, }; @@ -116,7 +110,6 @@ static const struct qcom_ubwc_cfg_data sm6115_data = { .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 14, }; @@ -139,7 +132,6 @@ static const struct qcom_ubwc_cfg_data sm6350_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 14, }; @@ -161,7 +153,6 @@ static const struct qcom_ubwc_cfg_data sm8250_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, .macrotile_mode = true, @@ -171,7 +162,6 @@ static const struct qcom_ubwc_cfg_data sm8350_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, .macrotile_mode = true, @@ -181,7 +171,6 @@ static const struct qcom_ubwc_cfg_data sm8550_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, .macrotile_mode = true, @@ -190,7 +179,6 @@ static const struct qcom_ubwc_cfg_data sm8550_data = { static const struct qcom_ubwc_cfg_data sm8750_data = { .ubwc_enc_version = UBWC_5_0, .ubwc_swizzle = 6, - .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, .macrotile_mode = true, @@ -199,7 +187,6 @@ static const struct qcom_ubwc_cfg_data sm8750_data = { static const struct qcom_ubwc_cfg_data glymur_data = { .ubwc_enc_version = UBWC_5_0, .ubwc_swizzle = 0, - .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, .macrotile_mode = true, diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index c5f049eab07d..405d83f8d95b 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -33,7 +33,6 @@ struct qcom_ubwc_cfg_data { * DDR bank. This should ideally use DRAM type detection. */ int highest_bank_bit; - bool ubwc_bank_spread; /** * @macrotile_mode: Macrotile Mode @@ -88,7 +87,7 @@ static inline bool qcom_ubwc_macrotile_mode(const struct qcom_ubwc_cfg_data *cfg static inline bool qcom_ubwc_bank_spread(const struct qcom_ubwc_cfg_data *cfg) { - return cfg->ubwc_bank_spread; + return true; } static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg) -- 2.47.3