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Wed, 11 Mar 2026 00:40:48 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9700.010; Wed, 11 Mar 2026 00:40:48 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Miguel Ojeda , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Dave Airlie , Daniel Almeida , Koen Koning , dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org, Nikola Djukic , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Alex Gaynor , Boqun Feng , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Balbir Singh , Philipp Stanner , Elle Rhumsaa , alexeyi@nvidia.com, Eliot Courtney , joel@joelfernandes.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH v9 14/23] gpu: nova-core: mm: Add unified page table entry wrapper enums Date: Tue, 10 Mar 2026 20:39:59 -0400 Message-Id: <20260311004008.2208806-15-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260311004008.2208806-1-joelagnelf@nvidia.com> References: <20260311004008.2208806-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: BLAPR03CA0065.namprd03.prod.outlook.com (2603:10b6:208:329::10) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|BY5PR12MB4051:EE_ X-MS-Office365-Filtering-Correlation-Id: 8aeca5c3-8948-43aa-1dbf-08de7f06d6b4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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These enums allow the page table walker and VMM to work with both MMU versions. Each unified type: - Takes MmuVersion parameter in constructors - Wraps both ver2 and ver3 variants - Delegates method calls to the appropriate variant This enables version-agnostic page table operations while keeping version-specific implementation details encapsulated in the ver2 and ver3 modules. Cc: Nikola Djukic Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable.rs | 322 ++++++++++++++++++++++++++ 1 file changed, 322 insertions(+) diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/mm/pagetable.rs index 5c6ae78506af..8cc5f72ead11 100644 --- a/drivers/gpu/nova-core/mm/pagetable.rs +++ b/drivers/gpu/nova-core/mm/pagetable.rs @@ -12,6 +12,13 @@ pub(crate) mod ver3; use crate::gpu::Architecture; +use crate::mm::{ + pramin, + Pfn, + VirtualAddress, + VramAddress, // +}; +use kernel::prelude::*; /// Extracts the page table index at a given level from a virtual address. pub(crate) trait VaLevelIndex { @@ -84,6 +91,96 @@ pub(crate) const fn as_index(&self) -> u64 { } } +impl MmuVersion { + /// Get the `PDE` levels (excluding PTE level) for page table walking. + pub(crate) fn pde_levels(&self) -> &'static [PageTableLevel] { + match self { + Self::V2 => ver2::PDE_LEVELS, + Self::V3 => ver3::PDE_LEVELS, + } + } + + /// Get the PTE level for this MMU version. + pub(crate) fn pte_level(&self) -> PageTableLevel { + match self { + Self::V2 => ver2::PTE_LEVEL, + Self::V3 => ver3::PTE_LEVEL, + } + } + + /// Get the dual PDE level (128-bit entries) for this MMU version. + pub(crate) fn dual_pde_level(&self) -> PageTableLevel { + match self { + Self::V2 => ver2::DUAL_PDE_LEVEL, + Self::V3 => ver3::DUAL_PDE_LEVEL, + } + } + + /// Get the number of PDE levels for this MMU version. + pub(crate) fn pde_level_count(&self) -> usize { + self.pde_levels().len() + } + + /// Get the entry size in bytes for a given level. + pub(crate) fn entry_size(&self, level: PageTableLevel) -> usize { + if level == self.dual_pde_level() { + 16 // 128-bit dual PDE + } else { + 8 // 64-bit PDE/PTE + } + } + + /// Get the number of entries per page table page for a given level. + pub(crate) fn entries_per_page(&self, level: PageTableLevel) -> usize { + match self { + Self::V2 => match level { + // TODO: Calculate these values from the bitfield dynamically + // instead of hardcoding them. + PageTableLevel::Pdb => 4, // PD3 root: bits [48:47] = 2 bits + PageTableLevel::L3 => 256, // PD0 dual: bits [28:21] = 8 bits + _ => 512, // PD2, PD1, PT: 9 bits each + }, + Self::V3 => match level { + PageTableLevel::Pdb => 2, // PDE4 root: bit [56] = 1 bit, 2 entries + PageTableLevel::L4 => 256, // PDE0 dual: bits [28:21] = 8 bits + _ => 512, // PDE3, PDE2, PDE1, PT: 9 bits each + }, + } + } + + /// Extract the page table index at `level` from `va` for this MMU version. + pub(crate) fn level_index(&self, va: VirtualAddress, level: u64) -> u64 { + match self { + Self::V2 => ver2::VirtualAddressV2::new(va).level_index(level), + Self::V3 => ver3::VirtualAddressV3::new(va).level_index(level), + } + } + + /// Compute upper bound on page table pages needed for `num_virt_pages`. + /// + /// Walks from PTE level up through PDE levels, accumulating the tree. + pub(crate) fn pt_pages_upper_bound(&self, num_virt_pages: usize) -> usize { + let mut total = 0; + + // PTE pages at the leaf level. + let pte_epp = self.entries_per_page(self.pte_level()); + let mut pages_at_level = num_virt_pages.div_ceil(pte_epp); + total += pages_at_level; + + // Walk PDE levels bottom-up (reverse of pde_levels()). + for &level in self.pde_levels().iter().rev() { + let epp = self.entries_per_page(level); + + // How many pages at this level do we need to point to + // the previous pages_at_level? + pages_at_level = pages_at_level.div_ceil(epp); + total += pages_at_level; + } + + total + } +} + /// Memory aperture for Page Table Entries (`PTE`s). /// /// Determines which memory region the `PTE` points to. @@ -156,3 +253,228 @@ fn from(val: AperturePde) -> Self { val as u8 } } + +/// Unified Page Table Entry wrapper for both MMU v2 and v3 `PTE` +/// types, allowing the walker to work with either format. +#[derive(Debug, Clone, Copy)] +pub(crate) enum Pte { + /// MMU v2 `PTE` (Turing/Ampere/Ada). + V2(ver2::Pte), + /// MMU v3 `PTE` (Hopper+). + V3(ver3::Pte), +} + +impl Pte { + /// Create a `PTE` from a raw `u64` value for the given MMU version. + pub(crate) fn new(version: MmuVersion, val: u64) -> Self { + match version { + MmuVersion::V2 => Self::V2(ver2::Pte::new(val)), + MmuVersion::V3 => Self::V3(ver3::Pte::new(val)), + } + } + + /// Create an invalid `PTE` for the given MMU version. + pub(crate) fn invalid(version: MmuVersion) -> Self { + match version { + MmuVersion::V2 => Self::V2(ver2::Pte::invalid()), + MmuVersion::V3 => Self::V3(ver3::Pte::invalid()), + } + } + + /// Create a valid `PTE` for video memory. + pub(crate) fn new_vram(version: MmuVersion, pfn: Pfn, writable: bool) -> Self { + match version { + MmuVersion::V2 => Self::V2(ver2::Pte::new_vram(pfn, writable)), + MmuVersion::V3 => Self::V3(ver3::Pte::new_vram(pfn, writable)), + } + } + + /// Check if this `PTE` is valid. + pub(crate) fn is_valid(&self) -> bool { + match self { + Self::V2(p) => p.valid(), + Self::V3(p) => p.valid(), + } + } + + /// Get the physical frame number. + pub(crate) fn frame_number(&self) -> Pfn { + match self { + Self::V2(p) => p.frame_number(), + Self::V3(p) => p.frame_number(), + } + } + + /// Get the raw `u64` value. + pub(crate) fn raw_u64(&self) -> u64 { + match self { + Self::V2(p) => p.raw_u64(), + Self::V3(p) => p.raw_u64(), + } + } + + /// Read a `PTE` from VRAM. + pub(crate) fn read( + window: &mut pramin::PraminWindow<'_>, + addr: VramAddress, + mmu_version: MmuVersion, + ) -> Result { + let val = window.try_read64(addr.raw())?; + Ok(Self::new(mmu_version, val)) + } + + /// Write this `PTE` to VRAM. + pub(crate) fn write(&self, window: &mut pramin::PraminWindow<'_>, addr: VramAddress) -> Result { + window.try_write64(addr.raw(), self.raw_u64()) + } +} + +/// Unified Page Directory Entry wrapper for both MMU v2 and v3 `PDE`. +#[derive(Debug, Clone, Copy)] +pub(crate) enum Pde { + /// MMU v2 `PDE` (Turing/Ampere/Ada). + V2(ver2::Pde), + /// MMU v3 `PDE` (Hopper+). + V3(ver3::Pde), +} + +impl Pde { + /// Create a `PDE` from a raw `u64` value for the given MMU version. + pub(crate) fn new(version: MmuVersion, val: u64) -> Self { + match version { + MmuVersion::V2 => Self::V2(ver2::Pde::new(val)), + MmuVersion::V3 => Self::V3(ver3::Pde::new(val)), + } + } + + /// Create a valid `PDE` pointing to a page table in video memory. + pub(crate) fn new_vram(version: MmuVersion, table_pfn: Pfn) -> Self { + match version { + MmuVersion::V2 => Self::V2(ver2::Pde::new_vram(table_pfn)), + MmuVersion::V3 => Self::V3(ver3::Pde::new_vram(table_pfn)), + } + } + + /// Create an invalid `PDE` for the given MMU version. + pub(crate) fn invalid(version: MmuVersion) -> Self { + match version { + MmuVersion::V2 => Self::V2(ver2::Pde::invalid()), + MmuVersion::V3 => Self::V3(ver3::Pde::invalid()), + } + } + + /// Check if this `PDE` is valid. + pub(crate) fn is_valid(&self) -> bool { + match self { + Self::V2(p) => p.is_valid(), + Self::V3(p) => p.is_valid(), + } + } + + /// Get the VRAM address of the page table. + pub(crate) fn table_vram_address(&self) -> VramAddress { + match self { + Self::V2(p) => p.table_vram_address(), + Self::V3(p) => p.table_vram_address(), + } + } + + /// Get the raw `u64` value. + pub(crate) fn raw_u64(&self) -> u64 { + match self { + Self::V2(p) => p.raw_u64(), + Self::V3(p) => p.raw_u64(), + } + } + + /// Read a `PDE` from VRAM. + pub(crate) fn read( + window: &mut pramin::PraminWindow<'_>, + addr: VramAddress, + mmu_version: MmuVersion, + ) -> Result { + let val = window.try_read64(addr.raw())?; + Ok(Self::new(mmu_version, val)) + } + + /// Write this `PDE` to VRAM. + pub(crate) fn write(&self, window: &mut pramin::PraminWindow<'_>, addr: VramAddress) -> Result { + window.try_write64(addr.raw(), self.raw_u64()) + } +} + +/// Unified Dual Page Directory Entry wrapper for both MMU v2 and v3 [`DualPde`]. +#[derive(Debug, Clone, Copy)] +pub(crate) enum DualPde { + /// MMU v2 [`DualPde`] (Turing/Ampere/Ada). + V2(ver2::DualPde), + /// MMU v3 [`DualPde`] (Hopper+). + V3(ver3::DualPde), +} + +impl DualPde { + /// Create a [`DualPde`] from raw 128-bit value (two `u64`s) for the given MMU version. + pub(crate) fn new(version: MmuVersion, big: u64, small: u64) -> Self { + match version { + MmuVersion::V2 => Self::V2(ver2::DualPde::new(big, small)), + MmuVersion::V3 => Self::V3(ver3::DualPde::new(big, small)), + } + } + + /// Create a [`DualPde`] with only the small page table pointer set. + pub(crate) fn new_small(version: MmuVersion, table_pfn: Pfn) -> Self { + match version { + MmuVersion::V2 => Self::V2(ver2::DualPde::new_small(table_pfn)), + MmuVersion::V3 => Self::V3(ver3::DualPde::new_small(table_pfn)), + } + } + + /// Check if the small page table pointer is valid. + pub(crate) fn has_small(&self) -> bool { + match self { + Self::V2(d) => d.has_small(), + Self::V3(d) => d.has_small(), + } + } + + /// Get the small page table VRAM address. + pub(crate) fn small_vram_address(&self) -> VramAddress { + match self { + Self::V2(d) => d.small.table_vram_address(), + Self::V3(d) => d.small.table_vram_address(), + } + } + + /// Get the raw `u64` value of the big PDE. + pub(crate) fn big_raw_u64(&self) -> u64 { + match self { + Self::V2(d) => d.big.raw_u64(), + Self::V3(d) => d.big.raw_u64(), + } + } + + /// Get the raw `u64` value of the small PDE. + pub(crate) fn small_raw_u64(&self) -> u64 { + match self { + Self::V2(d) => d.small.raw_u64(), + Self::V3(d) => d.small.raw_u64(), + } + } + + /// Read a dual PDE (128-bit) from VRAM. + pub(crate) fn read( + window: &mut pramin::PraminWindow<'_>, + addr: VramAddress, + mmu_version: MmuVersion, + ) -> Result { + let lo = window.try_read64(addr.raw())?; + let hi = window.try_read64(addr.raw() + 8)?; + Ok(Self::new(mmu_version, lo, hi)) + } + + /// Write this dual PDE (128-bit) to VRAM. + pub(crate) fn write(&self, window: &mut pramin::PraminWindow<'_>, addr: VramAddress) -> Result { + window.try_write64(addr.raw(), self.big_raw_u64())?; + window.try_write64(addr.raw() + 8, self.small_raw_u64()) + } +} -- 2.34.1