[PATCH 00/19] Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[PATCH 00/19] Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[Ankit Nautiyal]

Enable Adaptive Sync SDP for Panel replay + auxless ALPM.
First few patches are fixes in existing AS SDP enablement.
Later patches add the support to send AS SDP for Panel replay with Link
ON and with auxless ALPM (Link-Off). 

This series is in continuation from discussions in [1] [2] and more
recent [3]:

Apart from few patches from [3] new changes include:
- Some clean up in drm/dp Macros
- Add new DPCD bit to get FAVT PAYLOAD FIELDS PARSING SUPPORT.
- Add AS SDP version and PR and VRR specific bits in drm_dp.h.
- Modify AS SDP compute config to accomodate PR with Link On and Link
  Off.
- Program Downspread Ctrl DPCD bits.
- Make way for T1 and T2 AS SDP transmission timing/position.

[1] https://lore.kernel.org/all/1b8c6c6de1e5fe0db83e6ae942dfee7e6f950767.camel@intel.com/
[2] https://lore.kernel.org/all/aPtqdAxDwiuQZbrn@intel.com/
[3] https://lore.kernel.org/intel-gfx/7c2d6f4e-69e6-452a-89cc-5fd4254430bd@intel.com/T/#m6e8beab2cc3b6ff9d61f740f107d83a2f4e08114

Rev2:
 - Drop the redundant version member for AS SDP, and use the member
   revision
 - Drop member to store AS SDP transmission time, use simple helper
   instead.
 - Use Burst mode to write Panel Replay config DPCDs.
 - Split AS SDP configuration in compute_config() and
   compute_config_late() phase.
 - Always enable AS SDP whenever supported by source + sink.

Ankit Nautiyal (19):
  drm/dp: Rename and relocate AS SDP payload field masks
  drm/dp: Clean up DPRX feature enumeration macros
  drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support
  include/drm/display/dp: Add DPCD registers for configuring Panel
    Replay + VRR
  drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP
  drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink
  drm/i915/dp: Account for AS_SDP guardband only when enabled
  drm/i915/dp: Add a helper to decide if AS SDP can be used
  drm/i915/dp: Skip AS SDP for DP branch devices
  drm/i915/dp: Use revision field of AS SDP data structure
  drm/i915/dp: Add member to intel_dp to store AS SDP v2 support
  drm/i915/psr: Write the PR config DPCDs in burst mode
  drm/i915/display: Add helper for AS SDP transmission time selection
  drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission
    time
  drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless
    ALPM
  drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off
  drm/i915/dp: Split AS SDP computation between compute_config and
    compute_config_late
  drm/i915/dp: Make provision for AS SDP version 1
  drm/i915/dp: Always enable AS SDP if supported by source + sink

 drivers/gpu/drm/i915/display/intel_alpm.c     |  20 ++-
 drivers/gpu/drm/i915/display/intel_display.c  |   3 +-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 151 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_dp.h       |   2 +
 .../drm/i915/display/intel_dp_link_training.c |  10 +-
 .../drm/i915/display/intel_dp_link_training.h |   3 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  20 ++-
 drivers/gpu/drm/i915/display/intel_vrr.c      |  10 ++
 include/drm/display/drm_dp.h                  |  23 ++-
 11 files changed, 195 insertions(+), 50 deletions(-)

-- 
2.45.2

[PATCH 01/19] drm/dp: Rename and relocate AS SDP payload field masks

[Ankit Nautiyal]

The AS SDP payload field masks were misnamed and placed under the DPRX
feature enumeration list. These are not DPRX capability bits, but are
payload field masks for the Adaptive Sync SDP.

Relocate both masks next to the AS SDP definitions.
Update users to the corrected names. No functional change.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
 include/drm/display/drm_dp.h            | 5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fbb5e2f9c241..cd1539c3268c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5295,8 +5295,8 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
 		return -EINVAL;
 
-	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
-	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
+	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
+	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 8b15d3eeb716..4ea3b5b08a12 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1204,8 +1204,6 @@
 
 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
-# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE		GENMASK(1, 0)
-# define DP_ADAPTIVE_SYNC_SDP_LENGTH				GENMASK(5, 0)
 # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
 # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
 
@@ -1870,4 +1868,7 @@ enum operation_mode {
 	DP_AS_SDP_FAVT_TRR_REACHED = 0x03
 };
 
+#define DP_AS_SDP_OPERATION_MODE_MASK	GENMASK(1, 0)
+#define DP_AS_SDP_LENGTH_MASK		GENMASK(5, 0)
+
 #endif /* _DRM_DP_H_ */
-- 
2.45.2

[PATCH 02/19] drm/dp: Clean up DPRX feature enumeration macros

[Ankit Nautiyal]

Align the DP_DPRX feature enumeration macros for better readability and
consistency, and use the BIT() macro instead of open-coded shifts.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 4ea3b5b08a12..49f0154eb93c 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1202,10 +1202,10 @@
 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS	0x04
 # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS	0x05
 
-#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
-# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
-# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
-# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
+#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
+# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
+# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
+# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
 
 #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
 # define DP_UHBR10                             (1 << 0)
-- 
2.45.2

[PATCH 03/19] drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support

[Ankit Nautiyal]

DP v2.1 introduced support for sending AS SDP payload bytes for FAVT.
Add the relavant bits for the same.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 49f0154eb93c..8d172863eba3 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1205,6 +1205,7 @@
 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED						BIT(0)
 # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED	BIT(1)
+# define DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED			BIT(2) /* 2.1 */
 # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED				BIT(4)
 
 #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
-- 
2.45.2

[PATCH 04/19] drm/dp: Add DPCD for configuring AS SDP for PR + VRR

[Ankit Nautiyal]

Add additional DPCDs required to be configured to support VRR with Panel
Replay. These DPCDs are specifically required for configuring Adaptive Sync
SDP and are introduced in DP v2.1.

v2:
 - Correct the shift for the bits. (Ville)
 - Add DP_PR_ prefix for the PR-related fields.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 8d172863eba3..e6752a92d5dc 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -775,6 +775,15 @@
 # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)
 # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)
 
+#define PANEL_REPLAY_CONFIG3				0x11a /* DP 2.1 */
+# define DP_PR_AS_SDP_SETUP_TIME_SHIFT			6
+# define DP_PR_AS_SDP_SETUP_TIME_MASK			(3 << DP_PR_AS_SDP_SETUP_TIME_SHIFT)
+# define DP_PR_AS_SDP_SETUP_TIME_T1			0
+# define DP_PR_AS_SDP_SETUP_TIME_DYNAMIC		1 /* DP 2.1 Table 2-227 */
+# define DP_PR_AS_SDP_SETUP_TIME_T2			2
+# define DP_PR_AS_SDP_SETUP_TIME(t)			(((t) << DP_PR_AS_SDP_SETUP_TIME_SHIFT) & \
+							 DP_PR_AS_SDP_SETUP_TIME_MASK)
+
 #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
-- 
2.45.2

[PATCH 05/19] drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP

[Ankit Nautiyal]

Correct the bit-shift logic to properly readback the 10 bit target_rr from
DB3 and DB4.

v2: Align the style with readback for vtotal. (Ville)

Fixes: 12ea89291603 ("drm/i915/dp: Add Read/Write support for Adaptive Sync SDP")
Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cd1539c3268c..108d2e338e3a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5298,7 +5298,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
 	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
-	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
 
 	return 0;
-- 
2.45.2

[PATCH 06/19] drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink

[Ankit Nautiyal]

Currently we do not support VRR with HDMI so skip vrr compute
config step for all DP branch devices.

v2: Restrict VRR on all DP branch devices instead for checking only for
    HDMI. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8a957804cb97..160e1c24aa4b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -55,6 +55,16 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 		if (connector->mst.dp)
 			return false;
 		intel_dp = intel_attached_dp(connector);
+		/*
+		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
+		 * via a PCON could support VRR. However, supporting VRR through a
+		 * PCON requires non-trivial changes that are not implemented yet.
+		 * Until that support exists, avoid VRR on all DP branch devices.
+		 *
+		 * TODO: Add support for VRR for DP->HDMI 2.1 PCON.
+		 */
+		if (drm_dp_is_branch(intel_dp->dpcd))
+			return false;
 
 		if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
 			return false;
-- 
2.45.2

[PATCH 07/19] drm/i915/dp: Account for AS_SDP guardband only when enabled

[Ankit Nautiyal]

Currently the intel_dp_sdp_min_guardband() accounts for AS_SDP for all
platforms that support adaptive sync SDP even for configurations where
it cannot be enabled. Instead account for adaptive sync SDP guardband
only when it is enabled.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 108d2e338e3a..10927bc836d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7364,7 +7364,6 @@ int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 ty
 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 			       bool assume_all_enabled)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
 	int sdp_guardband = 0;
 
 	if (assume_all_enabled ||
@@ -7379,8 +7378,8 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS));
 
-	if ((assume_all_enabled && HAS_AS_SDP(display)) ||
-	    crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
+	if (crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC));
 
-- 
2.45.2

[PATCH 08/19] drm/i915/dp: Add a helper to decide if AS SDP can be used

[Ankit Nautiyal]

Add a helper that determines whether AS SDP can be used for the
current DP configuration. For now this is true only when the sink
supports AS SDP and VRR is enabled, but more conditions may be added
later.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 10927bc836d6..41908f68ffba 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3124,6 +3124,15 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
 	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
 }
 
+static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
+				    struct intel_crtc_state *crtc_state)
+{
+	if (!intel_dp->as_sdp_supported)
+		return false;
+
+	return crtc_state->vrr.enable;
+}
+
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -3131,7 +3140,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 
-	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
+	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
 		return;
 
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
-- 
2.45.2

[PATCH 09/19] drm/i915/dp: Skip AS SDP for DP branch devices

[Ankit Nautiyal]

Currently, VRR is not implmented for DP branch devices.
So skip sending AS SDP for them.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 41908f68ffba..17af68a1a9e5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3130,6 +3130,12 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
 	if (!intel_dp->as_sdp_supported)
 		return false;
 
+	/*
+	 * #TODO Implement AS SDP for DP branch device.
+	 */
+	if (drm_dp_is_branch(intel_dp->dpcd))
+		return false;
+
 	return crtc_state->vrr.enable;
 }
 
-- 
2.45.2

[PATCH 10/19] drm/i915/dp: Use revision field of AS SDP data structure

[Ankit Nautiyal]

Use the revision field of struct drm_dp_as_sdp instead of current
hardcoding for the AS SDP revisions.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
 drivers/gpu/drm/i915/display/intel_dp.c      | 7 +++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b18ce0c36a64..88e1b503d301 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4900,7 +4900,8 @@ static bool
 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
 			const struct drm_dp_as_sdp *b)
 {
-	return a->vtotal == b->vtotal &&
+	return a->revision == b->revision &&
+		a->vtotal == b->vtotal &&
 		a->target_rr == b->target_rr &&
 		a->duration_incr_ms == b->duration_incr_ms &&
 		a->duration_decr_ms == b->duration_decr_ms &&
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 17af68a1a9e5..0d2403d48528 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3154,6 +3154,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
 	as_sdp->length = 0x9;
 	as_sdp->duration_incr_ms = 0;
+	as_sdp->revision = 0x2;
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
 	if (crtc_state->cmrr.enable) {
@@ -5117,7 +5118,7 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
 	/* Prepare AS (Adaptive Sync) SDP Header */
 	sdp->sdp_header.HB0 = 0;
 	sdp->sdp_header.HB1 = as_sdp->sdp_type;
-	sdp->sdp_header.HB2 = 0x02;
+	sdp->sdp_header.HB2 = as_sdp->revision;
 	sdp->sdp_header.HB3 = as_sdp->length;
 
 	/* Fill AS (Adaptive Sync) SDP Payload */
@@ -5304,13 +5305,11 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
 		return -EINVAL;
 
-	if (sdp->sdp_header.HB2 != 0x02)
-		return -EINVAL;
-
 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
 		return -EINVAL;
 
 	as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK;
+	as_sdp->revision = sdp->sdp_header.HB2;
 	as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
-- 
2.45.2

[PATCH 11/19] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Ankit Nautiyal]

DP v2.1 mentions support for FAVT payload fields parsing in DPCD 0x2214
Bit 2. This essentially signals the support for AS SDP version 2, that
allows source to set the version in HB2[4:0] and the payload length in
HB3[5:0] of the AS SDP header.

Read this bit and store the AS SDP v2 capability in intel_dp.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 21 +++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e189f8c39ccb..d783cea06aed 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1870,6 +1870,7 @@ struct intel_dp {
 	/* connector directly attached - won't be use for modeset in mst world */
 	struct intel_connector *attached_connector;
 	bool as_sdp_supported;
+	bool as_sdp_v2_supported;
 
 	struct drm_dp_tunnel *tunnel;
 	bool tunnel_suspended:1;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0d2403d48528..e6148e7f0ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6291,6 +6291,24 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
 					       false);
 }
 
+static bool
+intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	u8 rx_features;
+
+	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
+				  DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
+				  &rx_features) < 0) {
+		drm_dbg_kms(display->drm,
+			    "Failed to read DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
+
+		return false;
+	}
+
+	return rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED;
+}
+
 static void
 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
 {
@@ -6298,6 +6316,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
 
 	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
 		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
+
+	intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
+					intel_dp_sink_supports_as_sdp_v2(intel_dp);
 }
 
 static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
-- 
2.45.2

[PATCH 12/19] drm/i915/psr: Write the PR config DPCDs in burst mode

[Ankit Nautiyal]

Replace the consecutive single-byte writes to PANEL_REPLAY_CONFIG and
CONFIG2 with one drm_dp_dpcd_write() burst starting at PANEL_REPLAY_CONFIG,
reducing AUX transactions.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5041a5a138d1..ee6e26abd05e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -774,27 +774,33 @@ static bool psr2_su_region_et_valid(struct intel_connector *connector, bool pane
 static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 				      const struct intel_crtc_state *crtc_state)
 {
-	u8 val = DP_PANEL_REPLAY_ENABLE |
+	struct intel_display *display = to_intel_display(intel_dp);
+	u8 panel_replay_config = DP_PANEL_REPLAY_ENABLE |
 		DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
 		DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
 		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
 		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
 	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
+	u8 buf[2];
+	int ret;
 
 	if (crtc_state->has_sel_update)
-		val |= DP_PANEL_REPLAY_SU_ENABLE;
+		panel_replay_config |= DP_PANEL_REPLAY_SU_ENABLE;
 
 	if (crtc_state->enable_psr2_su_region_et)
-		val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
+		panel_replay_config |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
 
 	if (crtc_state->req_psr2_sdp_prior_scanline)
 		panel_replay_config2 |=
 			DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
 
-	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
+	buf[0] = panel_replay_config;
+	buf[1] = panel_replay_config2;
+
+	ret = drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG, buf, sizeof(buf));
 
-	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
-			   panel_replay_config2);
+	if (ret < 0 || ret != sizeof(buf))
+		drm_dbg_kms(display->drm, "Failed to write Panel Replay Configs\n");
 }
 
 static void _psr_enable_sink(struct intel_dp *intel_dp,
-- 
2.45.2

[PATCH 13/19] drm/i915/display: Add helper for AS SDP transmission time selection

[Ankit Nautiyal]

AS SDP may be transmitted at T1 or T2 depending on Panel Replay and
Adaptive Sync SDP configuration as per DP 2.1. Current we are using
T1 only, but future PR/AS SDP modes/features may require T2 or dynamic
selection.

Introduce a helper to return the appropriate AS SDP transmission time so
that a single value is consistently used for programming PR_ALPM.
For now this returns T1.

v2: Avoid adding new member to crtc_state; use a helper. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 20 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.c   |  9 +++++++++
 drivers/gpu/drm/i915/display/intel_dp.h   |  2 ++
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index a7350ce8e716..0a6da3f926d3 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -11,6 +11,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_display_utils.h"
 #include "intel_dp.h"
 #include "intel_dp_aux.h"
 #include "intel_psr.h"
@@ -359,6 +360,23 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	crtc_state->has_lobf = true;
 }
 
+static int get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
+{
+	int as_sdp_setup_time = intel_dp_as_sdp_transmission_time();
+
+	switch (as_sdp_setup_time) {
+	case DP_PR_AS_SDP_SETUP_TIME_T1:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+	case DP_PR_AS_SDP_SETUP_TIME_DYNAMIC:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
+	case DP_PR_AS_SDP_SETUP_TIME_T2:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
+	default:
+		MISSING_CASE(as_sdp_setup_time);
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+	}
+}
+
 static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state)
 {
@@ -382,7 +400,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
 
 		if (intel_dp->as_sdp_supported) {
-			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
 
 			if (crtc_state->link_off_after_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e6148e7f0ebc..74a8af3cf18c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7439,3 +7439,12 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 	return true;
 }
+
+int intel_dp_as_sdp_transmission_time(void)
+{
+	/*
+	 * For now we use T1 as the transmission time.
+	 * This can be later changed as per requirements.
+	 */
+	return DP_PR_AS_SDP_SETUP_TIME_T1;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 2849b9ecdc71..2e4609d9d05c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
 		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
 
+int intel_dp_as_sdp_transmission_time(void);
+
 #endif /* __INTEL_DP_H__ */
-- 
2.45.2

[PATCH 14/19] drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time

[Ankit Nautiyal]

Panel Replay requires the AS SDP transmission time to be written into
PANEL_REPLAY_CONFIG3. This field was previously not programmed.

Use the AS SDP transmission-time helper to populate CONFIG3.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ee6e26abd05e..9add6e0d6f04 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -781,7 +781,8 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
 		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
 	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
-	u8 buf[2];
+	u8 panel_replay_config3 = DP_PR_AS_SDP_SETUP_TIME(intel_dp_as_sdp_transmission_time());
+	u8 buf[3];
 	int ret;
 
 	if (crtc_state->has_sel_update)
@@ -796,6 +797,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 
 	buf[0] = panel_replay_config;
 	buf[1] = panel_replay_config2;
+	buf[2] = panel_replay_config3;
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG, buf, sizeof(buf));
 
-- 
2.45.2

[PATCH 15/19] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

[Ankit Nautiyal]

To support Panel Replay with Auxless-ALPM, the source must transmit
Adaptive-Sync SDPs for video timing synchronization while PR is active.
As per the DP spec v2.1, this requires setting DPCD 0x0107[6]
(FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether VRR is enabled
(AVT/FAVT) or fixed-timing mode is used.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 ++++++++--
 drivers/gpu/drm/i915/display/intel_dp_link_training.h |  3 ++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c           |  2 +-
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 54c585c59b90..136cabf06fd9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -27,6 +27,7 @@
 #include <drm/display/drm_dp_helper.h>
 #include <drm/drm_print.h>
 
+#include "intel_alpm.h"
 #include "intel_display_core.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_types.h"
@@ -710,11 +711,14 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
 	return true;
 }
 
-void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
+void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
+				     bool is_vrr,
+				     bool is_pr_with_link_off)
 {
 	u8 link_config[2];
 
 	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
+	link_config[0] |= is_pr_with_link_off ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
 	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
 			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
@@ -737,7 +741,9 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
 	  * especially on the first real commit when clearing the inherited flag.
 	  */
 	intel_dp_link_training_set_mode(intel_dp,
-					crtc_state->port_clock, crtc_state->vrr.in_range);
+					crtc_state->port_clock,
+					crtc_state->vrr.in_range,
+					intel_alpm_is_alpm_aux_less(intel_dp, crtc_state));
 }
 
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 1ba22ed6db08..3591210f8ee6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
 bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
 
 void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
-				     int link_rate, bool is_vrr);
+				     int link_rate, bool is_vrr,
+				     bool is_pr_with_link_off);
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 				   int link_bw, int rate_select, int lane_count,
 				   bool enhanced_framing);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 887b6de14e46..2201cf7ce015 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -2142,7 +2142,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
 
 	intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
 
-	intel_dp_link_training_set_mode(intel_dp, link_rate, false);
+	intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);
 	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
 				      drm_dp_enhanced_frame_cap(intel_dp->dpcd));
 
-- 
2.45.2

[PATCH 16/19] drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off

[Ankit Nautiyal]

For Panel Replay with AUX-less ALPM (link-off PR), the source must send
Adaptive-Sync SDP v2. Program DB[1:0] per DP spec v2.1:
- VRR AVT: 00b (variable VTotal)
- VRR FAVT: 10b/11b (TRR not reached/reached)
- Fixed timing with PR link-off (VRR off): 01b (AS disabled; VTotal fixed)

Also, drop the redundant target_rr assignment.

v2: Fix the else case. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 74a8af3cf18c..2b0318e0ceb0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3161,9 +3161,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
 		as_sdp->target_rr_divider = true;
-	} else {
+	} else if (crtc_state->vrr.enable) {
 		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
-		as_sdp->target_rr = 0;
+	} else {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
 	}
 }
 
-- 
2.45.2

[PATCH 17/19] drm/i915/dp: Split AS SDP computation between compute_config and compute_config_late

[Ankit Nautiyal]

Currently we enable AS SDP only when VRR is enabled. As we start using
AS SDP for other features, this becomes a problem. The AS SDP
configuration can change dynamically based on VRR, CMRR, PR, ALPM, etc.
Since these features may be enabled or disabled after the initial
configuration, the AS SDP parameters need to be computed later in the
pipeline.

However, not all of the AS SDP logic can be moved to the late stage:
the VRR guardband optimization depends on knowing early whether AS SDP
can be used. Without this, we would end up accounting for AS SDP on all
platforms that support it, even for panels that do not support AS SDP.
Therefore we set the infoframe enable bit for AS SDP during
compute_config(), before the guardband is computed.

To handle these constraints, split the AS SDP programming into two
phases:

 - intel_dp_compute_as_sdp()
   Runs during compute_config().
   Sets only the infoframe enable bit so that the guardband logic can
   account for AS SDP requirements.

 - intel_dp_as_sdp_compute_config_late()
   Runs during compute_config_late().
   Computes all remaining AS SDP fields based on the features that need
   it.

The late-stage computation is called from
intel_dp_sdp_compute_config_late(), before computing the minimum guardband
for SDPs.

This is a preparatory change. A subsequent patch will always enable AS
SDP when the source and sink support it.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 67 ++++++++++++++++---------
 1 file changed, 44 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2b0318e0ceb0..4d0a7695be5a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3142,30 +3142,17 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
-	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
-
 	if (!intel_dp_can_use_as_sdp(intel_dp, crtc_state))
 		return;
 
+	/*
+	 * Only set the infoframes.enable flag here.
+	 * The remaining AS SDP fields are programmed in the
+	 * compute_config_late() phase. We need this flag early so that the
+	 * VRR guardband calculation can properly account for AS SDP
+	 * requirements.
+	 */
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
-
-	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
-	as_sdp->length = 0x9;
-	as_sdp->duration_incr_ms = 0;
-	as_sdp->revision = 0x2;
-	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
-
-	if (crtc_state->cmrr.enable) {
-		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
-		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
-		as_sdp->target_rr_divider = true;
-	} else if (crtc_state->vrr.enable) {
-		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
-	} else {
-		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
-	}
 }
 
 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
@@ -7344,11 +7331,45 @@ void intel_dp_mst_resume(struct intel_display *display)
 }
 
 static
-int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
+void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
+					 struct intel_crtc_state *crtc_state)
+{
+	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+
+	if ((crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) == 0)
+		return;
+
+	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
+	as_sdp->length = 0x9;
+	as_sdp->duration_incr_ms = 0;
+	as_sdp->revision = 0x2;
+	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
+
+	if (crtc_state->cmrr.enable) {
+		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
+		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
+		as_sdp->target_rr_divider = true;
+	} else if (crtc_state->vrr.enable) {
+		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
+	} else {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+	}
+}
+
+static
+int intel_dp_sdp_compute_config_late(struct intel_dp *intel_dp,
+				     struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	int guardband = intel_crtc_vblank_length(crtc_state);
-	int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
+	int min_sdp_guardband;
+
+	intel_dp_as_sdp_compute_config_late(intel_dp, crtc_state);
+
+	min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false);
 
 	if (guardband < min_sdp_guardband) {
 		drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",
@@ -7368,7 +7389,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 
 	intel_psr_compute_config_late(intel_dp, crtc_state);
 
-	ret = intel_dp_sdp_compute_config_late(crtc_state);
+	ret = intel_dp_sdp_compute_config_late(intel_dp, crtc_state);
 	if (ret)
 		return ret;
 
-- 
2.45.2

[PATCH 18/19] drm/i915/dp: Make provision for AS SDP version 1

[Ankit Nautiyal]

Currently we are setting AS SDP version to 2 without checking if the sink
supports it or whether we need to send version 1.

For PR with Link ON, the AS SDP version V1 is used.
When using AS SDP Version 1, AS SDP payload and parity bytes
are all set to zeroes.

Add a helper to compute the AS SDP version based on sink support and
feature requirement.

If AS SDP V2 is supported we use V2, unless Panel Replay with Link On is
enabled, for which we use V1.
If AS SDP V1 is not supported, we always send V1, without the payload.

Bspec: 75639
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4d0a7695be5a..6b45894e40e0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5109,6 +5109,10 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
 	sdp->sdp_header.HB2 = as_sdp->revision;
 	sdp->sdp_header.HB3 = as_sdp->length;
 
+	/* No Payload Data bytes for Version 1 */
+	if (as_sdp->revision == 0x1)
+		return length;
+
 	/* Fill AS (Adaptive Sync) SDP Payload */
 	sdp->db[0] = as_sdp->mode;
 	sdp->db[1] = as_sdp->vtotal & 0xFF;
@@ -7330,6 +7334,19 @@ void intel_dp_mst_resume(struct intel_display *display)
 	}
 }
 
+static bool intel_dp_get_as_sdp_revision(struct intel_dp *intel_dp,
+					 struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->has_panel_replay &&
+	    !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
+		return 1;
+
+	if (intel_dp->as_sdp_v2_supported)
+		return 2;
+
+	return 1;
+}
+
 static
 void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
 					 struct intel_crtc_state *crtc_state)
@@ -7345,7 +7362,12 @@ void intel_dp_as_sdp_compute_config_late(struct intel_dp *intel_dp,
 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
 	as_sdp->length = 0x9;
 	as_sdp->duration_incr_ms = 0;
-	as_sdp->revision = 0x2;
+	as_sdp->revision = intel_dp_get_as_sdp_revision(intel_dp, crtc_state);
+
+	/* No payload data bytes for Version 1 */
+	if (as_sdp->revision == 1)
+		return;
+
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
 	if (crtc_state->cmrr.enable) {
-- 
2.45.2

[PATCH 19/19] drm/i915/dp: Always enable AS SDP if supported by source + sink

[Ankit Nautiyal]

Currently AS SDP is only configured when VRR is enabled. However, other
use cases like CMRR, Panel Replay, etc. also send information to the sink
via AS SDPs.

With optimized guardband, we also need to account for wakeup time and other
relevant details that depend on the AS SDP position whenever AS SDP is
enabled. If a feature enabling AS SDP gets turned on later (after modeset),
the guardband might not be sufficient and may need to increase, triggering
a full modeset.

To avoid this, always send AS SDP whenever the source and sink both
support it.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6b45894e40e0..a9ee3d307b3b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3136,7 +3136,7 @@ static bool intel_dp_can_use_as_sdp(struct intel_dp *intel_dp,
 	if (drm_dp_is_branch(intel_dp->dpcd))
 		return false;
 
-	return crtc_state->vrr.enable;
+	return true;
 }
 
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
-- 
2.45.2

Claude review: Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[Claude Code Review Bot]

Overall Series Review

Subject: Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Patches: 20
Reviewed: 2026-03-12T06:55:27.715509

---

This 19-patch series from Ankit Nautiyal enables Adaptive Sync SDP for Panel Replay with Link ON and Auxless ALPM (Link-Off) on Intel display hardware. The first several patches clean up drm/dp header macros, fix existing bugs, and add preparatory infrastructure. Later patches add the actual PR+VRR AS SDP support, split AS SDP computation into early and late phases, and always enable AS SDP when source+sink support it.

The series is generally well-structured and incrementally builds the feature. Some patches have Ville's R-b, indicating they've had prior review. However, there is one **critical bug** in patch 14 involving an incorrect burst DPCD write, and several other issues worth addressing.

**Key issues:**
1. **Bug (Patch 14):** Burst write sends PANEL_REPLAY_CONFIG3 to wrong DPCD address (0x1b2 instead of 0x11a)
2. **Bug (Patch 18):** `intel_dp_get_as_sdp_revision()` returns `bool` but should return `int`/`u8`
3. **Patch ordering:** Patches 3 and 4 arrive out of order in the mbox (numbered 03/04 but message IDs -4 and -5 swapped)

---

---
Generated by Claude Code Patch Reviewer

Claude review: drm/dp: Rename and relocate AS SDP payload field masks

[Claude Code Review Bot]

Patch Review

Straightforward rename of `DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE` → `DP_AS_SDP_OPERATION_MODE_MASK` and `DP_ADAPTIVE_SYNC_SDP_LENGTH` → `DP_AS_SDP_LENGTH_MASK`, relocated from the DPRX feature enumeration section to near the AS SDP definitions. Users updated. No functional change.

Looks good.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/dp: Clean up DPRX feature enumeration macros

[Claude Code Review Bot]

Patch Review

Converts open-coded `(1 << N)` to `BIT(N)` and aligns the indentation of the `DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1` macros. Cosmetic cleanup.

**Minor nit:** The alignment results in very long lines for the `#define` of the register address itself:
```c
#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1					0x2214 /* 2.0 E11 */
```
This is significantly wider than surrounding definitions (e.g. `DP_128B132B_SUPPORTED_LINK_RATES` at line 370 still uses the old style). Inconsistency with surrounding code, but not a blocker.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support

[Claude Code Review Bot]

Patch Review

Adds `DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED` as `BIT(2)` at DPCD 0x2214. Fine.

**Minor:** Commit message has typo "relavant" → "relevant".

---
Generated by Claude Code Patch Reviewer

Claude review: drm/dp: Add DPCD for configuring AS SDP for PR + VRR

[Claude Code Review Bot]

Patch Review

Adds `PANEL_REPLAY_CONFIG3` at DPCD address `0x11a` with AS SDP setup time fields.

**Concern:** The `DP_PR_AS_SDP_SETUP_TIME()` macro uses a custom shift+mask pattern rather than the more idiomatic `FIELD_PREP()`:
```c
# define DP_PR_AS_SDP_SETUP_TIME(t)    (((t) << DP_PR_AS_SDP_SETUP_TIME_SHIFT) & \
                                         DP_PR_AS_SDP_SETUP_TIME_MASK)
```
Consider using `FIELD_PREP(DP_PR_AS_SDP_SETUP_TIME_MASK, t)` for consistency with modern kernel style, though the existing approach works correctly.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP

[Claude Code Review Bot]

Patch Review

Fixes the bit-shift bug in `intel_dp_as_sdp_unpack()`:
```c
-	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
```
The old code OR'd DB[4] bits 1:0 into bits 1:0 of the result, overwriting DB[3] bits. Correct fix. Has Ville's R-b. Should have `Cc: stable`.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink

[Claude Code Review Bot]

Patch Review

Disables VRR for all DP branch devices in `intel_vrr_is_capable()`, with a comment explaining that PCON VRR support is not yet implemented. Has Ville's R-b.

Looks good.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/dp: Account for AS_SDP guardband only when enabled

[Claude Code Review Bot]

Patch Review

Removes the `assume_all_enabled && HAS_AS_SDP(display)` check and only accounts for AS SDP guardband when it's actually enabled in `crtc_state->infoframes.enable`.

**Concern:** The `assume_all_enabled` parameter was presumably there for a reason — to conservatively compute guardbands during early configuration when individual SDP enables aren't yet known. By removing the AS SDP case from the `assume_all_enabled` path, this could under-count guardbands in scenarios where `assume_all_enabled=true` is passed. However, patch 19 later always enables AS SDP when supported, which may compensate. The ordering here means there's a window between patches 7 and 19 where guardbands could be under-counted.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/dp: Add a helper to decide if AS SDP can be used

[Claude Code Review Bot]

Patch Review

Introduces `intel_dp_can_use_as_sdp()` that checks `as_sdp_supported` and `vrr.enable`. Clean refactor.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/dp: Skip AS SDP for DP branch devices

[Claude Code Review Bot]

Patch Review

Adds a branch device check to `intel_dp_can_use_as_sdp()`.

**Minor nit:** The comment style `#TODO` is unusual for kernel code; the conventional style is simply `TODO:`:
```c
/*
 * #TODO Implement AS SDP for DP branch device.
 */
```

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/dp: Use revision field of AS SDP data structure

[Claude Code Review Bot]

Patch Review

Uses `as_sdp->revision` in pack/unpack instead of hardcoding `0x02`. Also adds revision to the comparison function and removes the HB2 == 0x02 validation check in unpack.

**Concern about removing validation:** The unpack function previously rejected AS SDPs with HB2 != 0x02. Now it accepts any revision. While this enables version 1 support later (patch 18), removing the validation entirely means any garbage revision value will be silently accepted. Consider adding a range check (revision == 1 || revision == 2).

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/dp: Add member to intel_dp to store AS SDP v2 support

[Claude Code Review Bot]

Patch Review

Reads `DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED` from DPCD 0x2214 and stores it as `as_sdp_v2_supported`. Clean.

**Minor:** The `drm_dp_dpcd_read_byte()` error check uses `< 0` but `drm_dp_dpcd_readb()` returns the number of bytes read (1 on success). Could check `!= 1` for robustness, though `< 0` catches actual errors.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/psr: Write the PR config DPCDs in burst mode

[Claude Code Review Bot]

Patch Review

Converts two `drm_dp_dpcd_writeb()` calls to a single burst `drm_dp_dpcd_write()` for PANEL_REPLAY_CONFIG (0x1b0) and CONFIG2 (0x1b1). Good optimization.

**Minor:** The error check `ret < 0 || ret != sizeof(buf)` — the `ret < 0` is redundant since `ret != sizeof(buf)` would also catch negative values. Not a bug, just slightly verbose.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/display: Add helper for AS SDP transmission time selection

[Claude Code Review Bot]

Patch Review

Adds `intel_dp_as_sdp_transmission_time()` which always returns `DP_PR_AS_SDP_SETUP_TIME_T1`, and `get_pr_alpm_as_sdp_transmission_time()` to translate it to hardware register values.

**Design concern:** `intel_dp_as_sdp_transmission_time()` takes no parameters and always returns T1. This is essentially a constant masquerading as a function. A `#define` or an inline returning a constant would be clearer. The commit message says "future PR/AS SDP modes/features may require T2 or dynamic selection" but designing for hypothetical requirements adds unnecessary indirection. Also, the `crtc_state` parameter to `get_pr_alpm_as_sdp_transmission_time()` is unused.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time

[Claude Code Review Bot]

Patch Review

**BUG:** This patch extends the burst write buffer from 2 to 3 bytes:
```c
u8 buf[3];
...
buf[0] = panel_replay_config;   // -> PANEL_REPLAY_CONFIG  (0x1b0)
buf[1] = panel_replay_config2;  // -> PANEL_REPLAY_CONFIG2 (0x1b1)
buf[2] = panel_replay_config3;  // -> 0x1b2 (WRONG!)
```

But `PANEL_REPLAY_CONFIG3` is defined (in patch 4) at DPCD address **0x11a**, not at 0x1b2. The burst write starting at `PANEL_REPLAY_CONFIG` (0x1b0) will write `panel_replay_config3` to address 0x1b2, which is an entirely different (and possibly reserved) DPCD register. **CONFIG3 must be written separately with its own `drm_dp_dpcd_writeb()` call to address 0x11a.**

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

[Claude Code Review Bot]

Patch Review

Extends `intel_dp_link_training_set_mode()` with a `is_pr_with_link_off` parameter to set `DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE` in DPCD 0x0107.

The condition used in `intel_dp_update_downspread_ctrl()` is:
```c
intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)
```
This checks if auxless ALPM is active, which implies PR with link-off. Seems correct per the spec reference.

**Concern about the condition:** The commit message says this bit should be set "whether VRR is enabled (AVT/FAVT) or fixed-timing mode is used", meaning any time PR+auxless-ALPM is active. But `intel_alpm_is_alpm_aux_less()` may return true even without AS SDP support. Should this be gated on AS SDP being available too?

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off

[Claude Code Review Bot]

Patch Review

Adds the fixed-vtotal mode (`DP_AS_SDP_AVT_FIXED_VTOTAL`) for the case where VRR is not enabled but AS SDP is still sent (for PR link-off). Also drops a redundant `as_sdp->target_rr = 0` assignment.

Looks correct.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/dp: Split AS SDP computation between compute_config and compute_config_late

[Claude Code Review Bot]

Patch Review

Splits AS SDP programming into early (just the enable bit) and late (all fields) phases. The rationale is well explained in the commit message: the guardband calculation needs the enable bit early, but the actual SDP fields depend on features computed later.

**Observation:** The `intel_dp_sdp_compute_config_late()` signature changes to accept `intel_dp`, which is a reasonable change. The approach is sound architecturally.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/dp: Make provision for AS SDP version 1

[Claude Code Review Bot]

Patch Review

**BUG:** `intel_dp_get_as_sdp_revision()` is declared as returning `bool` but returns integer values 1 or 2:
```c
static bool intel_dp_get_as_sdp_revision(struct intel_dp *intel_dp,
                                         struct intel_crtc_state *crtc_state)
{
    if (crtc_state->has_panel_replay &&
        !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
        return 1;
    if (intel_dp->as_sdp_v2_supported)
        return 2;
    return 1;
}
```
With `bool` return type, both 1 and 2 would be truncated to `true` (1), so `as_sdp->revision` would always be 1. The return type **must** be `int` or `u8`.

Also, the commit message is slightly confusing: "If AS SDP V1 is not supported, we always send V1, without the payload." — should this say "If AS SDP V2 is not supported"?

**Concern:** In the pack function, version 1 skips the payload:
```c
if (as_sdp->revision == 0x1)
    return length;
```
But `length` is computed as `sizeof(struct dp_sdp)` which includes headers and all DB bytes. For V1 with no payload, should this return just the header size? The current code returns the full struct size but doesn't fill DB bytes — the caller may still transmit garbage in the payload area depending on how `length` is used.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/i915/dp: Always enable AS SDP if supported by source + sink

[Claude Code Review Bot]

Patch Review

Changes `intel_dp_can_use_as_sdp()` to return `true` whenever AS SDP is supported (regardless of VRR), removing the `crtc_state->vrr.enable` check.

This is the culmination of the series. Combined with the split compute phases (patch 17), the late compute will determine the actual SDP fields based on which features are active.

**This looks correct** given the preparatory work, though it means AS SDP will be sent even on configurations where no VRR/PR/CMRR feature needs it (just with AVT_FIXED_VTOTAL mode).

---
Generated by Claude Code Patch Reviewer