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Thu, 12 Mar 2026 01:28:40 -0700 (PDT) Received: from [127.0.1.1] ([2a04:6f00:1::ee:b:1015]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439fe219c41sm6273780f8f.29.2026.03.12.01.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 01:28:40 -0700 (PDT) From: Jun Nie Date: Thu, 12 Mar 2026 16:28:11 +0800 Subject: [PATCH v19 2/4] drm/msm/dpu: Defer SSPP allocation until CRTC check MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260312-msm-next-quad-pipe-split-v19-2-4ffa2b06c996@linaro.org> References: <20260312-msm-next-quad-pipe-split-v19-0-4ffa2b06c996@linaro.org> In-Reply-To: <20260312-msm-next-quad-pipe-split-v19-0-4ffa2b06c996@linaro.org> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Clark , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773304094; l=10582; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=llcAoN5oMCj08hUSIdLT6NP8xPSgK+elXOWbE1sjvd8=; b=ObM16Q5nSNb6OskbUYeeMtfFvDsy/YRjzDsHTsWSpTqbAcocUYuxFSX+LmAVArbQeMPZXms/F 7C/Fus0C+7AAVDlPA2W4pFo5hC7O8rWJl4Q8VL2dM6blSK+y52r53FK X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently, mapping plane to SSPP occurs during the plane check phase for non-virtual plane case. The SSPP allocation and plane mapping occurs during CRTC check phase for virtual plane case. Defer these SSPP operations until CRTC check stage to unify the 2 cases, and ease later revisement for quad-pipe change. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 25 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 136 ++++++++++++++---------------- 2 files changed, 80 insertions(+), 81 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 6bf7c46379aed..e97456d4fbb8c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1325,7 +1325,7 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) return false; } -static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) +static int dpu_crtc_assign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) { int total_planes = crtc->dev->mode_config.num_total_plane; struct drm_atomic_state *state = crtc_state->state; @@ -1338,8 +1338,6 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state if (IS_ERR(global_state)) return PTR_ERR(global_state); - dpu_rm_release_all_sspp(global_state, crtc); - if (!crtc_state->enable) return 0; @@ -1366,6 +1364,19 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state return ret; } +static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) +{ + struct dpu_global_state *global_state; + + global_state = dpu_kms_get_global_state(crtc_state->state); + if (IS_ERR(global_state)) + return PTR_ERR(global_state); + + dpu_rm_release_all_sspp(global_state, crtc); + + return dpu_crtc_assign_planes(crtc, crtc_state); +} + #define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE #define MAX_HDISPLAY_SPLIT 1080 @@ -1534,9 +1545,11 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, return rc; } - if (dpu_use_virtual_planes && - (crtc_state->planes_changed || crtc_state->zpos_changed)) { - rc = dpu_crtc_reassign_planes(crtc, crtc_state); + if (crtc_state->planes_changed || crtc_state->zpos_changed) { + if (dpu_use_virtual_planes) + rc = dpu_crtc_reassign_planes(crtc, crtc_state); + else + rc = dpu_crtc_assign_planes(crtc, crtc_state); if (rc < 0) return rc; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 4ed14f203c315..70992a4401d69 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1112,65 +1112,13 @@ static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate, static int dpu_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) -{ - struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, - plane); - int ret = 0; - struct dpu_plane *pdpu = to_dpu_plane(plane); - struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); - struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); - struct dpu_sw_pipe *pipe = &pstate->pipe[0]; - struct dpu_sw_pipe *r_pipe = &pstate->pipe[1]; - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0]; - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1]; - const struct drm_crtc_state *crtc_state = NULL; - uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth; - - if (new_plane_state->crtc) - crtc_state = drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); - - pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - - if (!pipe->sspp) - return -EINVAL; - - ret = dpu_plane_atomic_check_nosspp(plane, new_plane_state, crtc_state); - if (ret) - return ret; - - if (!new_plane_state->visible) - return 0; - - ret = dpu_plane_split(plane, new_plane_state, crtc_state); - if (ret) - return ret; - - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, - pipe->sspp, - msm_framebuffer_format(new_plane_state->fb), - max_linewidth)) { - DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT - " max_line:%u, can't use split source\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), - DRM_RECT_ARG(&r_pipe_cfg->src_rect), - max_linewidth); - return -E2BIG; - } - - return dpu_plane_atomic_check_sspp(plane, state, crtc_state); -} - -static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) { struct drm_plane_state *plane_state = drm_atomic_get_plane_state(state, plane); struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); - struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); + int ret = 0; struct drm_crtc_state *crtc_state = NULL; - int ret, i; if (IS_ERR(plane_state)) return PTR_ERR(plane_state); @@ -1183,20 +1131,8 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, if (ret) return ret; - if (!plane_state->visible) { - /* - * resources are freed by dpu_crtc_assign_plane_resources(), - * but clean them here. - */ - for (i = 0; i < PIPES_PER_PLANE; i++) - pstate->pipe[i].sspp = NULL; - + if (!plane_state->visible) return 0; - } - - ret = dpu_plane_split(plane, plane_state, crtc_state); - if (ret) - return ret; /* * Force resource reallocation if the format of FB or src/dst have @@ -1211,7 +1147,6 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, msm_framebuffer_format(old_plane_state->fb) != msm_framebuffer_format(plane_state->fb)) crtc_state->planes_changed = true; - return 0; } @@ -1258,9 +1193,9 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, struct dpu_global_state *global_state, struct drm_atomic_state *state, struct drm_plane_state *plane_state, + const struct drm_crtc_state *crtc_state, struct drm_plane_state **prev_adjacent_plane_state) { - const struct drm_crtc_state *crtc_state = NULL; struct drm_plane *plane = plane_state->plane; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); struct dpu_rm_sspp_requirements reqs; @@ -1270,10 +1205,6 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, const struct msm_format *fmt; int i, ret; - if (plane_state->crtc) - crtc_state = drm_atomic_get_new_crtc_state(state, - plane_state->crtc); - pstate = to_dpu_plane_state(plane_state); for (i = 0; i < STAGES_PER_PLANE; i++) prev_adjacent_pstate[i] = prev_adjacent_plane_state[i] ? @@ -1285,6 +1216,10 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, if (!plane_state->fb) return -EINVAL; + ret = dpu_plane_split(plane, plane_state, crtc_state); + if (ret) + return ret; + fmt = msm_framebuffer_format(plane_state->fb); reqs.yuv = MSM_FORMAT_IS_YUV(fmt); reqs.scale = (plane_state->src_w >> 16 != plane_state->crtc_w) || @@ -1315,14 +1250,55 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, return dpu_plane_atomic_check_sspp(plane, state, crtc_state); } +static int dpu_plane_assign_resources(struct drm_crtc *crtc, + struct dpu_global_state *global_state, + struct drm_atomic_state *state, + struct drm_plane_state *plane_state, + const struct drm_crtc_state *crtc_state) +{ + struct drm_plane *plane = plane_state->plane; + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); + struct dpu_sw_pipe *pipe = &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe = &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1]; + struct dpu_plane *pdpu = to_dpu_plane(plane); + int ret; + + pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + if (!pipe->sspp) + return -EINVAL; + + ret = dpu_plane_split(plane, plane_state, crtc_state); + if (ret) + return ret; + + if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, + pipe->sspp, + msm_framebuffer_format(plane_state->fb), + dpu_kms->catalog->caps->max_linewidth)) { + DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT + " max_line:%u, can't use split source\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), + DRM_RECT_ARG(&r_pipe_cfg->src_rect), + dpu_kms->catalog->caps->max_linewidth); + return -E2BIG; + } + + return dpu_plane_atomic_check_sspp(plane, state, crtc_state); +} + int dpu_assign_plane_resources(struct dpu_global_state *global_state, struct drm_atomic_state *state, struct drm_crtc *crtc, struct drm_plane_state **states, unsigned int num_planes) { - unsigned int i; struct drm_plane_state *prev_adjacent_plane_state[STAGES_PER_PLANE] = { NULL }; + const struct drm_crtc_state *crtc_state = NULL; + unsigned int i; + int ret; for (i = 0; i < num_planes; i++) { struct drm_plane_state *plane_state = states[i]; @@ -1331,8 +1307,18 @@ int dpu_assign_plane_resources(struct dpu_global_state *global_state, !plane_state->visible) continue; - int ret = dpu_plane_virtual_assign_resources(crtc, global_state, + if (plane_state->crtc) + crtc_state = drm_atomic_get_new_crtc_state(state, + plane_state->crtc); + + if (!dpu_use_virtual_planes) + ret = dpu_plane_assign_resources(crtc, global_state, + state, plane_state, + crtc_state); + else + ret = dpu_plane_virtual_assign_resources(crtc, global_state, state, plane_state, + crtc_state, prev_adjacent_plane_state); if (ret) return ret; @@ -1769,7 +1755,7 @@ static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { static const struct drm_plane_helper_funcs dpu_plane_virtual_helper_funcs = { .prepare_fb = dpu_plane_prepare_fb, .cleanup_fb = dpu_plane_cleanup_fb, - .atomic_check = dpu_plane_virtual_atomic_check, + .atomic_check = dpu_plane_atomic_check, .atomic_update = dpu_plane_atomic_update, }; -- 2.43.0