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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67d617e1sm8646671fa.9.2026.03.12.06.30.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 06:30:07 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 12 Mar 2026 15:29:43 +0200 Subject: [PATCH v3 22/27] soc: qcom: ubwc: drop ubwc_dec_version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260312-ubwc-rework-v3-22-b7e8f800176a@oss.qualcomm.com> References: <20260312-ubwc-rework-v3-0-b7e8f800176a@oss.qualcomm.com> In-Reply-To: <20260312-ubwc-rework-v3-0-b7e8f800176a@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8046; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=LSluZwsJdsGyaDROP5csbwtPVQCwJHNeWkTj020h790=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpsr+4l3Ko26/Y3svi3Oy2rMDak0u4jXAac41JU 8oQWrSgN2+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCabK/uAAKCRCLPIo+Aiko 1WCLCACGiptIVN8WwsXvOgrRnbl7l5jkpiuG/ToAYoSX00jIBZj9xuGmTrQ7ck6xyWPOva21EIJ MBAFgUcKU6zS5vdxj8B2cMJvZmg/uUxNLa7UL4tcjjJw2bQpQtK4NLJukngS/8gyq9qtLP+cB+T GW5wQWKZe6SdZxBdf8yIT5TMHj35fCRWqe096yuujGItur284+oTCVsop8dM78Pj/8jumfoqmfo aDaZDFy+8miqkqX41dnLgu1XEWCO06pm0l6gxjfCIkIvSb1kMTPl+yNsYwRkabXWv94Pw7kgRl3 7sYfqV/PKRKUcRrPs6iXfkqV7ckbcWeDSvcV9xeW46ofsl/B X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEyMDEwNyBTYWx0ZWRfX8rVnA0eyb7v9 1Ropr+tk/R4Mn7QNeHSbq5G/Z0D4xnGCpwUOj5Nduf/lRF3wOrAxXjV1cM+m6uPCd3rqXhwIdSd 4QvJfWSkXme/gW45Cx6MFPpQO++/r5unCrlQJrq+jhqJGiYOz8pv990gh0RvPoxi6iFjbWlSNtW IbdGVOb/lcVukbXOUtzbx7eSG/31z9vGfp9dQjb1OuydVdOoEcPvzl3zkKNPV6RxJdDFs08mI// NTEKgATzGy/BGZCF8Ps58knI9DX5TgK9ECSTPSzgdlYYmiylroONTSlDUgIxuw1lS47Bblo7xfG QBrAIHahFDORice71mef8YsOd4zHjd2SXg3jJgn/NhsA6RsLV1dohuMd6TKKNdIElArTs3btCej u1Z9t5H2B4ZqYYyiwyMNLoH9wFqEwiHFCargai8bwcgmI/Rv7/xNDhtAfK7+uL18oyRUi9S8ayS AhzXWM7reeEubJuIx8w== X-Proofpoint-ORIG-GUID: y1HEWJKueaiH6SaS5w6M5gzfeqvCl2bi X-Authority-Analysis: v=2.4 cv=C+7kCAP+ c=1 sm=1 tr=0 ts=69b2bfe1 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=LGEa-qlQBoucZRe8vqkA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-GUID: y1HEWJKueaiH6SaS5w6M5gzfeqvCl2bi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-12_01,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603120107 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The ubwc_dec_version field has been inherited from the MDSS driver and it is equal to the version of the UBWC decoder in the display block only. Other IP Cores can have different UBWC decoders and so the version would vary between blocks. As the value is no longer used as is not relevant to other UBWC database consumers, drop it from the UBWC database. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/ubwc_config.c | 22 ---------------------- include/linux/soc/qcom/ubwc.h | 2 -- 2 files changed, 24 deletions(-) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index e63daf748e30..c5c7fcb4d013 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -18,7 +18,6 @@ static const struct qcom_ubwc_cfg_data no_ubwc_data = { static const struct qcom_ubwc_cfg_data kaanapali_data = { .ubwc_enc_version = UBWC_6_0, - .ubwc_dec_version = UBWC_6_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, @@ -28,7 +27,6 @@ static const struct qcom_ubwc_cfg_data kaanapali_data = { static const struct qcom_ubwc_cfg_data msm8937_data = { .ubwc_enc_version = UBWC_1_0, - .ubwc_dec_version = UBWC_1_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, @@ -37,7 +35,6 @@ static const struct qcom_ubwc_cfg_data msm8937_data = { static const struct qcom_ubwc_cfg_data msm8998_data = { .ubwc_enc_version = UBWC_1_0, - .ubwc_dec_version = UBWC_1_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, @@ -51,7 +48,6 @@ static const struct qcom_ubwc_cfg_data qcm2290_data = { static const struct qcom_ubwc_cfg_data sa8775p_data = { .ubwc_enc_version = UBWC_4_0, - .ubwc_dec_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, .highest_bank_bit = 13, @@ -60,7 +56,6 @@ static const struct qcom_ubwc_cfg_data sa8775p_data = { static const struct qcom_ubwc_cfg_data sar2130p_data = { .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */ - .ubwc_dec_version = UBWC_4_3, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, @@ -70,7 +65,6 @@ static const struct qcom_ubwc_cfg_data sar2130p_data = { static const struct qcom_ubwc_cfg_data sc7180_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, @@ -79,7 +73,6 @@ static const struct qcom_ubwc_cfg_data sc7180_data = { static const struct qcom_ubwc_cfg_data sc7280_data = { .ubwc_enc_version = UBWC_3_0, - .ubwc_dec_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, @@ -89,7 +82,6 @@ static const struct qcom_ubwc_cfg_data sc7280_data = { static const struct qcom_ubwc_cfg_data sc8180x_data = { .ubwc_enc_version = UBWC_3_0, - .ubwc_dec_version = UBWC_3_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 16, @@ -98,7 +90,6 @@ static const struct qcom_ubwc_cfg_data sc8180x_data = { static const struct qcom_ubwc_cfg_data sc8280xp_data = { .ubwc_enc_version = UBWC_4_0, - .ubwc_dec_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, @@ -108,7 +99,6 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data = { static const struct qcom_ubwc_cfg_data sdm670_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, @@ -116,7 +106,6 @@ static const struct qcom_ubwc_cfg_data sdm670_data = { static const struct qcom_ubwc_cfg_data sdm845_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 15, @@ -124,7 +113,6 @@ static const struct qcom_ubwc_cfg_data sdm845_data = { static const struct qcom_ubwc_cfg_data sm6115_data = { .ubwc_enc_version = UBWC_1_0, - .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, @@ -134,7 +122,6 @@ static const struct qcom_ubwc_cfg_data sm6115_data = { static const struct qcom_ubwc_cfg_data sm6125_data = { .ubwc_enc_version = UBWC_1_0, - .ubwc_dec_version = UBWC_3_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, @@ -143,7 +130,6 @@ static const struct qcom_ubwc_cfg_data sm6125_data = { static const struct qcom_ubwc_cfg_data sm6150_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, @@ -151,7 +137,6 @@ static const struct qcom_ubwc_cfg_data sm6150_data = { static const struct qcom_ubwc_cfg_data sm6350_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, @@ -160,7 +145,6 @@ static const struct qcom_ubwc_cfg_data sm6350_data = { static const struct qcom_ubwc_cfg_data sm7150_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, @@ -168,7 +152,6 @@ static const struct qcom_ubwc_cfg_data sm7150_data = { static const struct qcom_ubwc_cfg_data sm8150_data = { .ubwc_enc_version = UBWC_3_0, - .ubwc_dec_version = UBWC_3_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 15, @@ -176,7 +159,6 @@ static const struct qcom_ubwc_cfg_data sm8150_data = { static const struct qcom_ubwc_cfg_data sm8250_data = { .ubwc_enc_version = UBWC_4_0, - .ubwc_dec_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, @@ -187,7 +169,6 @@ static const struct qcom_ubwc_cfg_data sm8250_data = { static const struct qcom_ubwc_cfg_data sm8350_data = { .ubwc_enc_version = UBWC_4_0, - .ubwc_dec_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, @@ -198,7 +179,6 @@ static const struct qcom_ubwc_cfg_data sm8350_data = { static const struct qcom_ubwc_cfg_data sm8550_data = { .ubwc_enc_version = UBWC_4_0, - .ubwc_dec_version = UBWC_4_3, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, @@ -209,7 +189,6 @@ static const struct qcom_ubwc_cfg_data sm8550_data = { static const struct qcom_ubwc_cfg_data sm8750_data = { .ubwc_enc_version = UBWC_5_0, - .ubwc_dec_version = UBWC_5_0, .ubwc_swizzle = 6, .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ @@ -219,7 +198,6 @@ static const struct qcom_ubwc_cfg_data sm8750_data = { static const struct qcom_ubwc_cfg_data glymur_data = { .ubwc_enc_version = UBWC_5_0, - .ubwc_dec_version = UBWC_5_0, .ubwc_swizzle = 0, .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index 0b5aa9d0343b..c3f9efae5db8 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -13,8 +13,6 @@ struct qcom_ubwc_cfg_data { u32 ubwc_enc_version; - /* Can be read from MDSS_BASE + 0x58 */ - u32 ubwc_dec_version; /** * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling. -- 2.47.3