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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67d617e1sm8646671fa.9.2026.03.12.06.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 06:30:12 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 12 Mar 2026 15:29:46 +0200 Subject: [PATCH v3 25/27] soc: qcom: ubwc: use fixed values for UBWC swizzle for UBWC < 4.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260312-ubwc-rework-v3-25-b7e8f800176a@oss.qualcomm.com> References: <20260312-ubwc-rework-v3-0-b7e8f800176a@oss.qualcomm.com> In-Reply-To: <20260312-ubwc-rework-v3-0-b7e8f800176a@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6082; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=Qu7SCbd08U0FxPNSARkgsOS6vFM+FAyy6vsMyoASvXA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpsr+4mKKhz4P253cyaZOGYWl46uL+Qn4OOtS8h lh2uw5D9NeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCabK/uAAKCRCLPIo+Aiko 1RWRCACJ7gDjMdRfrJBykdoGT9vzRU982M9SLzPBR1PaPDZ0Jnn7Aoriafu7jdgUdgUPCD+XK3n XO5EdIDxSWiSGKwhTa/AawvYsjEAmAI/9ec7TOlTxOw4ODf/i/Ooh45lRmhGvCbQFJAbVb0XfLs 2mY2+s1c0N2SdFzQ5CzpsvjpnZu4EM/sMjKFtBoyzm7rcmffl2pceUMts4eDJyc/ab9ajJxO0Vq IgSsYPspLbX8RETu2YtsvzPJAm3OT2SwKvEtTxiovg6xi5CsB+2QdZyi9ijTGH6LNW96Bas3KQi 4BSkPXWJT31aI4PkObeGcM0q+3QEQQLbUQju9fzJAwCEik7Q X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: 6fySIhQvcl95cMBThMkJx3P8WgJp_M6Y X-Authority-Analysis: v=2.4 cv=IIIPywvG c=1 sm=1 tr=0 ts=69b2bfe6 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=8a_ODPMxA7UucN5sxwIA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEyMDEwNyBTYWx0ZWRfXxATTXtP9I6HX sfep8XsOYRIbDzUyYtNP4Un3VMgjv9nDKGynMN2+IjXuPFM6j5MJy2P/iqRLBHQPfjLMKHM9nJX 0VpbHIs5Bie9SBpQnYQ32VFYRGdsZh+nZfn2bRuaicq0BnPajfV39nIrtaenlzixBaDlbqgcPDb LrgUTVXx5XSkl0ogWrbfOVQ7HyCdN9Z98EwGnwjvVOkN7wuBt+zYTuyYmQb5dSTZ9zomtey7UXY hIXoXF3ri6iNieVps+QjQCDJXSqk9kFVXY7Wu2JsB0J7Se0PVDYY2rYOPUawTjYr7rYFwPo5tDH 3+3i6QxPva14ifsX2NJh+LXRS5Ld3Zxu8cYViZT5dQxOgsA++tUCbp48Zggm8yCfYast/EF4fLy G3itAN1/iZ9lO40/dt0L47X5PVHgoqavZtW1OJUJRMgrsmVQpsFqvcdUjep/sqqULn+Q1oTDcAy jDk595unZvNJ9fOqsAQ== X-Proofpoint-ORIG-GUID: 6fySIhQvcl95cMBThMkJx3P8WgJp_M6Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-12_01,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 impostorscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603120107 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" UBWC devices before 4.0 use standard UBWC swizzle levels. As all the drivers now use the qcom_ubwc_swizzle() helper, move those values to the helper, leaving UBWC 4.0+ intact for now. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/ubwc_config.c | 34 ---------------------------------- include/linux/soc/qcom/ubwc.h | 33 ++++++++++++++++++++++++--------- 2 files changed, 24 insertions(+), 43 deletions(-) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 51de36f5f40b..49edfabb5e18 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -25,17 +25,11 @@ static const struct qcom_ubwc_cfg_data kaanapali_data = { static const struct qcom_ubwc_cfg_data msm8937_data = { .ubwc_enc_version = UBWC_1_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data msm8998_data = { .ubwc_enc_version = UBWC_1_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 15, }; @@ -52,94 +46,66 @@ static const struct qcom_ubwc_cfg_data sa8775p_data = { static const struct qcom_ubwc_cfg_data sar2130p_data = { .ubwc_enc_version = UBWC_3_1, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 13, }; static const struct qcom_ubwc_cfg_data sc7180_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data sc7280_data = { .ubwc_enc_version = UBWC_3_1, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data sc8180x_data = { .ubwc_enc_version = UBWC_3_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 16, }; static const struct qcom_ubwc_cfg_data sc8280xp_data = { .ubwc_enc_version = UBWC_4_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 16, }; static const struct qcom_ubwc_cfg_data sdm670_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data sdm845_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 15, }; static const struct qcom_ubwc_cfg_data sm6115_data = { .ubwc_enc_version = UBWC_1_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data sm6125_data = { .ubwc_enc_version = UBWC_1_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | - UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data sm6150_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data sm6350_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data sm7150_data = { .ubwc_enc_version = UBWC_2_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; static const struct qcom_ubwc_cfg_data sm8150_data = { .ubwc_enc_version = UBWC_3_0, - .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | - UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 15, }; diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index fee778360ac2..7c9506741001 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -22,9 +22,6 @@ struct qcom_ubwc_cfg_data { * UBWC 4.0 adds the optional ability to disable levels 2 & 3. */ u32 ubwc_swizzle; -#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0) -#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1) -#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2) /** * @highest_bank_bit: Highest Bank Bit @@ -55,12 +52,7 @@ static inline const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void) static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data *cfg) { - bool ret = cfg->ubwc_enc_version == UBWC_1_0; - - if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1)) - pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0\n"); - - return ret; + return cfg->ubwc_enc_version == UBWC_1_0; } static inline bool qcom_ubwc_min_acc_length_64b(const struct qcom_ubwc_cfg_data *cfg) @@ -85,8 +77,31 @@ static inline bool qcom_ubwc_bank_spread(const struct qcom_ubwc_cfg_data *cfg) return true; } +#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0) +#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1) +#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2) + +/** + * @qcom_ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling. + * + * UBWC 1.0 always enables all three levels. + * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3. + * UBWC 4.0 adds the optional ability to disable levels 2 & 3. + */ static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg) { + if (cfg->ubwc_enc_version == 0) + return 0; + + if (cfg->ubwc_enc_version == UBWC_1_0) + return UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3; + + if (cfg->ubwc_enc_version < UBWC_4_0) + return UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3; + return cfg->ubwc_swizzle; } -- 2.47.3