From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1FB13103E2EB for ; Thu, 12 Mar 2026 13:29:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D99C110EA1C; Thu, 12 Mar 2026 13:29:47 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.b="mgZcgscQ"; dkim=pass (2048-bit key; unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="XHMB1gmo"; dkim-atps=neutral Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id B535C10EA0C for ; Thu, 12 Mar 2026 13:29:42 +0000 (UTC) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62C7drLo509557 for ; Thu, 12 Mar 2026 13:29:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wdo2GXNLuey4il0IRDIYFRsck7+hcgeJ1IZK0URwteg=; b=mgZcgscQ02PjXWUx xdt+c8cv9/ydhBJ1TAhJl7H6Iy5889y0cZ6zTCSYz5+vH1/TNSIbXhSBF5Dr5jQc uETYOU8W5ZqwnFL2wh2KC7mIGTcSTWGMZHfXnPJE3LM/WAWKzY6e8ohXc4qeTzbk KnXaZEjeWeWWkvBRsqz0BUrep+IQqGY1kTIsgkVsGETOPuq52poNGWNi976EJ26k a9D1fEWv0DQAYl6Kvv8V7GUfvZUNbkyhK2iTyVeANyix5Nib2DV4jaGFpgswy/bI zBtVEjG6kldLfN700lIP6rJ7IqY7S+Wi0a1aQlZWVq0CocKTgBD46N8tNatpkwpv e0387g== Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cus9w0vb6-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 12 Mar 2026 13:29:41 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-8cb6291d95aso1087635085a.1 for ; Thu, 12 Mar 2026 06:29:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773322181; x=1773926981; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wdo2GXNLuey4il0IRDIYFRsck7+hcgeJ1IZK0URwteg=; b=XHMB1gmoT1Ac5USB22EuuRVs7EzRR6z78CWgV+6aoBitYEPhfO+R6qTw69xn9NMa9B HkrXoOmBkOoMM1MplnmofhTaGPt9cwbnMsGFHoTQnV+/j7gugccBbc5QmCjdLOScXFNS fRMxeJON0dd/HG9mYu0iergJcRLiWkGPIGTi+x9YRHSo9nAbaLgm+VxAWswTgeCSybri 9IZzsQNGku2XJqpT3Vm3r0DbEWVajamTe7YHKKKqZCZP1aWEobF+CDyFooodq30l2fiI f7HzMqH0d8gIH09J0YIKNrsu4vUxz3Bh5M4YMcjmN1QnE3Nv/MAw6OufaEbQNohFTapW OnBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773322181; x=1773926981; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=wdo2GXNLuey4il0IRDIYFRsck7+hcgeJ1IZK0URwteg=; b=AgNDCwFiM50F5wa+pN4hShRFTKufSbaozq7iWg7l0iEKGQjo1C36Us3a4mHMjL/pj+ eoiHqu7wwTj63vzywtb2OKycAX73wIaUoK/bJwAvARveZzllXW7DoUa/zzA3lfbOp+vs LO++5pfU6P7IqBFU8a6tzcIt9k008IGPFQusZ0r3R+TlNiXJtUC2D5zyxNicEVC2zqPK Z+/xeSCxukkdcUlI/7ymxCAGowtTtn3HAzvP9HbnUHzROF0dFamrH6QUoTAmDl5dST5U YjVn7dfjl2RVxPtiak7R7GQ2DpcyABQZSgleSmxjeD4uSfC5ShWZfVYmy57zHVe43v3y +POQ== X-Forwarded-Encrypted: i=1; AJvYcCV/RWj7PqAtRLSbj06wyK3NJBA2yikWFyMBuY6fd4HKQun12AkuX6eN/do1Mu+Vwplxrev2FZ6/1rY=@lists.freedesktop.org X-Gm-Message-State: AOJu0YyW5fWuhUVLUdKbFN2B9QKIWfG4NMP9mW+EPm9CkZhiq6t1SkS5 NNU0CB91ji+gT4ZLFBu9uMh2DSJyoO9n+0nVkM5bFHyi6x5JZwcp8PlXTJVogpH6CuQLptLenaR nSTWqU5jOYYoxXv8+mrI7Bb+YjTbzf0Udxf+nUOWMy7OzYmCRF+c4Z6CK9Y4cGZbZjdIUc7w= X-Gm-Gg: ATEYQzw7+BaiBfTMfsr7o7WR5dnBmjJ8TVH9/VHdiqiirQ+a810np7AU0OcXFbmndce 3lcmGjKR4Pf/c79BKHYUJwPVUAIzGy9mxTxhGlngYogCd0GHszJps3IbHGYPJHcg5euzrDWzch3 ZSrvIdyVjLoFOhlCNMjD5YygYjVBC5kZ3iHy9ShRndmX9F2TWvyStjleCq32SEjWpy8vPuZ8lXp /DU72B0W6oJBH5ZCOfA/KmHXtFw0SvW+8orEZicOyuvHRjw6sc5OUIfWsTVDq6IqqEfgZY74vye 4/8JRP6IywKRQL2YKZ0EIlw2UR+Pp1F/5VmRnEDrBhDU0s80H2C3FkMPeHTDrSTp9K6u8D/riZ4 McjcxwuGYQDL4VrhrKJ+0lC/jQrR06Oye46EBeufxenr4P5KeWLasdIk/wDJH4Hm1GX2hEgg/29 nUL6QOvq5IsaYZyVO9oRR5+LKnFHkDASlAeY0= X-Received: by 2002:a05:620a:410d:b0:8cd:7811:9418 with SMTP id af79cd13be357-8cda1a88115mr853817285a.45.1773322180966; Thu, 12 Mar 2026 06:29:40 -0700 (PDT) X-Received: by 2002:a05:620a:410d:b0:8cd:7811:9418 with SMTP id af79cd13be357-8cda1a88115mr853810885a.45.1773322180342; Thu, 12 Mar 2026 06:29:40 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67d617e1sm8646671fa.9.2026.03.12.06.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 06:29:39 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 12 Mar 2026 15:29:26 +0200 Subject: [PATCH v3 05/27] drm/msm/adreno: Trust the SSoT UBWC config MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260312-ubwc-rework-v3-5-b7e8f800176a@oss.qualcomm.com> References: <20260312-ubwc-rework-v3-0-b7e8f800176a@oss.qualcomm.com> In-Reply-To: <20260312-ubwc-rework-v3-0-b7e8f800176a@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5880; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=E5AQkqpaNuM1RXBAxJ/mn1wbVur7sOZpcfQb1l6t7DE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpsr+1ZZ1VL0esfykadZwLa20M9PyGGoGxQofe4 2145JtAJhmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCabK/tQAKCRCLPIo+Aiko 1X69B/4wo2C/IzVyMnnSwpzQ/jCwMuw8tqFrJpiAekQksRWYKMAAbH1gSHDbCCcpEs8QScqudu0 Y2W/GMoXe8sEuxooXs4fEyzPHR7/lPCcSnHUmxcznTrsm5Wu/y6Llxg3dfFNLi9eg7w3bx+g+7i v5cLkcYyzchUo+HVgSYPLIxIi4G6RmAa5BzSGSq5a6Vyk8BtnHFdTeLnvDHKzhyeIlAu0XA082/ x2YiGE1j8AyuAtAkS7y3nharboer8I66eVcS9pu5V5yv+yzJCbIsCittxDXIC5QVCJiZp+SiMg6 cK7/9q+pA48OVjPavOUt/4/FTDXSbELmAaCus4S5sk+iXJwx X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: 0Zqh5MSCUcq2NTc1WY-dr5GECB_h_W1M X-Authority-Analysis: v=2.4 cv=IIIPywvG c=1 sm=1 tr=0 ts=69b2bfc5 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=IhcC-CrlSmvFA89tYH4A:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEyMDEwNyBTYWx0ZWRfX5aMZ580xeONb gmRF1X2fmv5gyiEwyYrMpWHHTAuQQjJi3nlwyjUA306sccNlwUn27qTJ0ehkKg5wLv9MYogX3Cb BmsGISRDh3R0cTbpdJbB3sMRU1Z1eiElyL7s2QJSMGKnWDPrSxGOw/PzS8uCeeGCt1VvJuUtjpA FZXQVoZ1IKmbbZ7Qvmwr/lz+Hmde8feHzybrD1O0Of94YlCzm6Bf7V8eDiLx+YeAQ+ZdSsYKPOb lvVb2s9Cpgi0Z2DMIYrxrYjq+xVVZp/HQDr5XTbCqBkAnN2zgcHKpbzeEIYtStXTMmIra3qrGlD HeHSO+FegqfmydUAhwGMp++eb1hO0F3WreddISNt4bepQQ/EaZiB10+WrdmpVpL7nTM9MAhoW20 W23ruUZ9MfEZeHYdrZrZvoQXsDLh+3ZX4iEsoNKcMSInN+OGzZWuo6PChEyjpUOELQ+Hjv7RpX+ ivMVNDGTjuS35qAYpCg== X-Proofpoint-ORIG-GUID: 0Zqh5MSCUcq2NTc1WY-dr5GECB_h_W1M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-12_01,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 impostorscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603120107 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Konrad Dybcio Now that the highest_bank_bit value is retrieved from the running system and the global config has been part of the tree for a couple of releases, there is no reason to keep any hardcoded values inside the GPU driver. Get rid of them. Signed-off-by: Konrad Dybcio Reviewed-by: Rob Clark Reviewed-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 ++--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 ++------------------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 -- 3 files changed, 6 insertions(+), 92 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index ef9fd6171af7..513557741677 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1727,7 +1727,6 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) struct msm_drm_private *priv = dev->dev_private; struct platform_device *pdev = priv->gpu_pdev; struct adreno_platform_config *config = pdev->dev.platform_data; - const struct qcom_ubwc_cfg_data *common_cfg; struct a5xx_gpu *a5xx_gpu = NULL; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; @@ -1765,13 +1764,9 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) a5xx_preempt_init(gpu); /* Inherit the common config and make some necessary fixups */ - common_cfg = qcom_ubwc_config_get_data(); - if (IS_ERR(common_cfg)) - return ERR_CAST(common_cfg); - - /* Copy the data into the internal struct to drop the const qualifier (temporarily) */ - adreno_gpu->_ubwc_config = *common_cfg; - adreno_gpu->ubwc_config = &adreno_gpu->_ubwc_config; + adreno_gpu->ubwc_config = qcom_ubwc_config_get_data(); + if (IS_ERR(adreno_gpu->ubwc_config)) + return ERR_CAST(adreno_gpu->ubwc_config); adreno_gpu->uche_trap_base = 0x0001ffffffff0000ull; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index d6dfe6337bc3..6eca7888013b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -729,82 +729,6 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); } -static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) -{ - const struct qcom_ubwc_cfg_data *common_cfg; - struct qcom_ubwc_cfg_data *cfg = &gpu->_ubwc_config; - - /* Inherit the common config and make some necessary fixups */ - common_cfg = qcom_ubwc_config_get_data(); - if (IS_ERR(common_cfg)) - return PTR_ERR(common_cfg); - - /* Copy the data into the internal struct to drop the const qualifier (temporarily) */ - *cfg = *common_cfg; - - /* Use common config as is for A8x */ - if (!adreno_is_a8xx(gpu)) { - cfg->ubwc_swizzle = 0x6; - cfg->highest_bank_bit = 15; - } - - if (adreno_is_a610(gpu)) { - cfg->highest_bank_bit = 13; - cfg->ubwc_swizzle = 0x7; - } - - if (adreno_is_a612(gpu)) - cfg->highest_bank_bit = 14; - - if (adreno_is_a618(gpu)) - cfg->highest_bank_bit = 14; - - if (adreno_is_a619(gpu)) - /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */ - cfg->highest_bank_bit = 13; - - if (adreno_is_a619_holi(gpu)) - cfg->highest_bank_bit = 13; - - if (adreno_is_a621(gpu)) - cfg->highest_bank_bit = 13; - - if (adreno_is_a623(gpu)) - cfg->highest_bank_bit = 16; - - if (adreno_is_a650(gpu) || - adreno_is_a660(gpu) || - adreno_is_a690(gpu) || - adreno_is_a730(gpu) || - adreno_is_a740_family(gpu)) { - /* TODO: get ddr type from bootloader and use 15 for LPDDR4 */ - cfg->highest_bank_bit = 16; - } - - if (adreno_is_a663(gpu)) { - cfg->highest_bank_bit = 13; - cfg->ubwc_swizzle = 0x4; - } - - if (adreno_is_7c3(gpu)) - cfg->highest_bank_bit = 14; - - if (adreno_is_a702(gpu)) - cfg->highest_bank_bit = 14; - - if (cfg->highest_bank_bit != common_cfg->highest_bank_bit) - DRM_WARN_ONCE("Inconclusive highest_bank_bit value: %u (GPU) vs %u (UBWC_CFG)\n", - cfg->highest_bank_bit, common_cfg->highest_bank_bit); - - if (cfg->ubwc_swizzle != common_cfg->ubwc_swizzle) - DRM_WARN_ONCE("Inconclusive ubwc_swizzle value: %u (GPU) vs %u (UBWC_CFG)\n", - cfg->ubwc_swizzle, common_cfg->ubwc_swizzle); - - gpu->ubwc_config = &gpu->_ubwc_config; - - return 0; -} - static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -2721,10 +2645,10 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu, adreno_gpu->funcs->mmu_fault_handler); - ret = a6xx_calc_ubwc_config(adreno_gpu); - if (ret) { + adreno_gpu->ubwc_config = qcom_ubwc_config_get_data(); + if (IS_ERR(adreno_gpu->ubwc_config)) { a6xx_destroy(&(a6xx_gpu->base.base)); - return ERR_PTR(ret); + return ERR_CAST(adreno_gpu->ubwc_config); } /* Set up the preemption specific bits and pieces for each ringbuffer */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 1d0145f8b3ec..da9a6da7c108 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -237,12 +237,7 @@ struct adreno_gpu { /* firmware: */ const struct firmware *fw[ADRENO_FW_MAX]; - /* - * The migration to the central UBWC config db is still in flight - keep - * a copy containing some local fixups until that's done. - */ const struct qcom_ubwc_cfg_data *ubwc_config; - struct qcom_ubwc_cfg_data _ubwc_config; /* * Register offsets are different between some GPUs. -- 2.47.3