From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5049D108E1F7 for ; Thu, 19 Mar 2026 11:58:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A4C4010E9A4; Thu, 19 Mar 2026 11:58:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; secure) header.d=pm.me header.i=@pm.me header.b="CL7/GhWa"; dkim-atps=neutral Received: from mail-10630.protonmail.ch (mail-10630.protonmail.ch [79.135.106.30]) by gabe.freedesktop.org (Postfix) with ESMTPS id 127B110E9A3 for ; Thu, 19 Mar 2026 11:58:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773921486; x=1774180686; bh=o9A8V2N6oCWL2uEYqKxQQ9YkXJRzeIHenXvajLxOdHI=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=CL7/GhWauv06VTKSKXH0j2wvtTWlShxLzBP1R99jqRJKcKKA00yLKBqG3hBqKYNOW /B3LI7vNasYp/o6udzkRgbCFEvOtYLOz9/XQJ2N6zDKUsjeZ752mJ0Ar83JIKRp3oi x4ztO7Vlq6FZSjMBpsD/DDmXArDOwu6kdmgcy3hzg+ETLc6XWa1KmHBPCkBwWrdXRG jl2GvmaIbru9TvuqygXX6HCz0W0O8khw+809u/rKUOtlxLV9rfw5TT3D7hwCWlZX8c F2asJsOGzmIMBvArwwlGCAq0fAgP3Zi4R0EdpEQgzPgrZhIXfKgVzTjxZ5j2VdvIjd 0qF7BtU8nvxRg== Date: Thu, 19 Mar 2026 11:58:01 +0000 To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Jeffrey Hugo From: Alexander Koskovich Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich Subject: [PATCH v3 4/4] drm/msm/dpu: fix video mode DSC INTF timing width calculation Message-ID: <20260319-dsi-rgb101010-support-v3-4-85b99df2d090@pm.me> In-Reply-To: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> References: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: d81a0ea6272180f431473f1ede9984010f0a9144 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Using bits_per_component * 3 as the divisor for the compressed INTF timing width produces constant FIFO errors for the BOE BF068MWM-TD0 panel due to bits_per_component being 10 which results in a divisor of 30 instead of 24. Regardless of the compression ratio and pixel depth, 24 bits of compressed data are transferred per pclk, so the divisor should always be 24. Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 0ba777bda253..5419ef0be137 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -122,19 +122,18 @@ static void drm_mode_to_intf_timing_params( =09} =20 =09/* -=09 * for DSI, if compression is enabled, then divide the horizonal active -=09 * timing parameters by compression ratio. bits of 3 components(R/G/B) -=09 * is compressed into bits of 1 pixel. +=09 * For DSI, if DSC is enabled, 24 bits of compressed data are +=09 * transferred per pclk regardless of the source pixel depth. =09 */ =09if (phys_enc->hw_intf->cap->type !=3D INTF_DP && timing->compression_en= ) { =09=09struct drm_dsc_config *dsc =3D =09=09 dpu_encoder_get_dsc_config(phys_enc->parent); + =09=09/* =09=09 * TODO: replace drm_dsc_get_bpp_int with logic to handle =09=09 * fractional part if there is fraction =09=09 */ -=09=09timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) / -=09=09=09=09(dsc->bits_per_component * 3); +=09=09timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) / 24; =09=09timing->xres =3D timing->width; =09} } --=20 2.53.0