From: Biju <biju.das.au@gmail.com>
To: Biju Das <biju.das.jz@bp.renesas.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>
Cc: Chris Brandt <chris.brandt@renesas.com>,
Hugo Villeneuve <hugo@hugovil.com>,
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,
Sam Ravnborg <sam@ravnborg.org>,
dri-devel@lists.freedesktop.org,
linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Biju Das <biju.das.au@gmail.com>
Subject: [PATCH v2 3/4] drm: renesas: rzg2l_mipi_dsi: Fix deassert of CMN_RSTB signal
Date: Thu, 19 Mar 2026 16:48:27 +0000 [thread overview]
Message-ID: <20260319164833.409126-4-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20260319164833.409126-1-biju.das.jz@bp.renesas.com>
From: Biju Das <biju.das.jz@bp.renesas.com>
The RZ/G2L hardware manual (Rev. 1.50, May 2025), Section 34.4.2.1,
requires deasserting the CMN_RSTB signal after setting the Link
registers. Move the reset_control_deassert() call from
rzg2l_mipi_dsi_dphy_init() to rzg2l_mipi_dsi_startup(), placing it
after the Link register writes. This reset signal is optional for
RZ/V2H SoCs, so add a NULL check. Drop the unused ret variable from
rzg2l_mipi_dsi_dphy_init().
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Updated commit header and description
* Moved the code from rzg2l_mipi_dsi_dphy_init() to rzg2l_mipi_dsi_startup()
* Moved the check before calling reset_control_deassert(), so that it will be
skipped for RZ/V2H SoC
---
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
index d2da247abf05..5020be0f72ac 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
@@ -484,7 +484,6 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
u32 dphytim1;
u32 dphytim2;
u32 dphytim3;
- int ret;
/* All DSI global operation timings are set with recommended setting */
for (i = 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) {
@@ -524,12 +523,6 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM2, dphytim2);
rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM3, dphytim3);
- ret = reset_control_deassert(dsi->rstc);
- if (ret < 0)
- return ret;
-
- udelay(1);
-
return 0;
}
@@ -809,6 +802,14 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
FIELD_MODIFY(DSISETR_MRPSZ, &dsisetr, RZG2L_DCS_BUF_SIZE);
rzg2l_mipi_dsi_link_write(dsi, DSISETR, dsisetr);
+ if (dsi->rstc) {
+ ret = reset_control_deassert(dsi->rstc);
+ if (ret < 0)
+ goto err_phy;
+
+ udelay(1);
+ }
+
return 0;
err_phy:
--
2.43.0
next prev parent reply other threads:[~2026-03-19 16:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-19 16:48 [PATCH v2 0/4] Improvements on RZ/G2L MIPI DSI driver Biju
2026-03-19 16:48 ` [PATCH v2 1/4] drm: renesas: rzg2l_mipi_dsi: Move rzg2l_mipi_dsi_set_display_timing() Biju
2026-03-21 18:12 ` Claude review: " Claude Code Review Bot
2026-03-19 16:48 ` [PATCH v2 2/4] drm: renesas: rzg2l_mipi_dsi: Fix assert of CMN_RSTB signal Biju
2026-03-21 18:12 ` Claude review: " Claude Code Review Bot
2026-03-19 16:48 ` Biju [this message]
2026-03-21 18:12 ` Claude review: drm: renesas: rzg2l_mipi_dsi: Fix deassert " Claude Code Review Bot
2026-03-19 16:48 ` [PATCH v2 4/4] drm: renesas: rzg2l_mipi_dsi: Increase reset deassertion delay to 1 msec Biju
2026-03-21 18:12 ` Claude review: " Claude Code Review Bot
2026-03-21 18:12 ` Claude review: Improvements on RZ/G2L MIPI DSI driver Claude Code Review Bot
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