[PATCH RESEND v2 0/2] Fixes and enhancements for Exynos (7870) DSIM bridge driver

[PATCH RESEND v2 0/2] Fixes and enhancements for Exynos (7870) DSIM bridge driver

[Kaustabh Chakraborty]

Since v6.17, there is a regression for the Exynos 7870 DSIM driver. The
display occasionally had random aberration when the panel was turned on.
The first patch addresses that.

The second patch replaces an implicit loop for waiting for PLL
stabilization with an interrupt-based solution, which should be more
reliable. This solution was suggested by Inki Dae in a discussion of an
earlier patch series sent by me. For further details, refer to its
commit description.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
Changes in v2:
- drop now-not-required [v1 1/3] (Marek Szyprowski)
- Link to v1: https://lore.kernel.org/r/20260124-exynos-dsim-fixes-v1-0-122d047a23d1@disroot.org

---
Kaustabh Chakraborty (2):
      drm/bridge: samsung-dsim: enable MFLUSH_VS for Exynos 7870 DSIM
      drm/bridge: samsung-dsim: use DSIM interrupt to wait for PLL stability

 drivers/gpu/drm/bridge/samsung-dsim.c | 48 +++++++++++++++++++++++++----------
 include/drm/bridge/samsung-dsim.h     |  1 +
 2 files changed, 35 insertions(+), 14 deletions(-)
---
base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
change-id: 20260124-exynos-dsim-fixes-5383d6a6f073

Best regards,
-- 
Kaustabh Chakraborty <kauschluss@disroot.org>

[PATCH RESEND v2 1/2] drm/bridge: samsung-dsim: enable MFLUSH_VS for Exynos 7870 DSIM

[Kaustabh Chakraborty]

Commit a36c533ad3e1 ("drm/bridge: samsung-dsim: Always flush display
FIFO on vsync pulse") intends to enable FIFO flushing at v-sync pulse by
not setting the active-low MFLUSH_VS bit.

However, in Exynos 7870 DSIM, the MFLUSH_VS bit is active-high. There is
no publicly available documentation to the best of my knowledge, but
downstream kernel code [1] supports this claim. Enable the bit for
Exynos 7870.

Cc: stable@vger.kernel.org # v6.17 and later
Link: https://github.com/samsungexynos7870/android_kernel_samsung_exynos7870/blob/a3762bb1761ae/drivers/video/fbdev/exynos/decon_7870/dsim_reg_7870.c#L699 [1]
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 1d85e706c74b9..70f8946ad3b24 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1089,6 +1089,13 @@ static int samsung_dsim_init_link(struct samsung_dsim *dsi)
 			reg |= DSIM_HBP_DISABLE_MODE;
 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
 			reg |= DSIM_HSA_DISABLE_MODE;
+
+		/*
+		 * For some hardware types, DSIM_MFLUSH_VS bit needs to be
+		 * enabled explicitly.
+		 */
+		if (dsi->plat_data->hw_type == DSIM_TYPE_EXYNOS7870)
+			reg |= DSIM_MFLUSH_VS;
 	}
 
 	if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)

-- 
2.53.0

[PATCH RESEND v2 2/2] drm/bridge: samsung-dsim: use DSIM interrupt to wait for PLL stability

[Kaustabh Chakraborty]

Stabilizing PLL needs to be waited for. This is done using a loop,
checking the PLL_STABLE bit in the status register.

DSIM fires an interrupt when the PLL is stabilized. Rely on this
functionality for stabilization wait, getting rid of the implicit loop.

This has been tested on a Galaxy J6 (Exynos 7870). Unfortunately, since
testing on all supported devices is less feasible, introduce a stop-gap
measure where the timeout has a gracious lower bound of 100
microseconds. This will (hopefully) prevent regressions due to timeout
on other devices.

Suggested-by: Inki Dae <inki.dae@samsung.com>
Link: https://lore.kernel.org/r/CAAQKjZMLMbwDVZRb5+Xb_5yz3AEP4uuzFJMuuZy9NFDu13VU5w@mail.gmail.com
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 41 +++++++++++++++++++++++------------
 include/drm/bridge/samsung-dsim.h     |  1 +
 2 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 70f8946ad3b24..0ca6c6484c9a6 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -17,6 +17,7 @@
 #include <linux/export.h>
 #include <linux/irq.h>
 #include <linux/media-bus-format.h>
+#include <linux/minmax.h>
 #include <linux/of.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
@@ -788,7 +789,7 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
 {
 	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
 	unsigned long fin, fout;
-	int timeout;
+	unsigned int timeout;
 	u8 p, s;
 	u16 m;
 	u32 reg;
@@ -849,19 +850,26 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
 	if (dsi->swap_dn_dp_data)
 		reg |= DSIM_PLL_DPDNSWAP_DAT;
 
+	/*
+	 * The PLL_TIMER value is the product of the timeout delay and the APB
+	 * bus clock rate. Calcutate the timeout delay on-the-fly here.
+	 * It is assumed that the bus clock is the first clock in the provided
+	 * bulk clock data.
+	 */
+	timeout = 100;
+	fin = clk_get_rate(dsi->driver_data->clk_data[0].clk) / HZ_PER_MHZ;
+	if (fin)
+		timeout = max(dsi->driver_data->reg_values[PLL_TIMER] / fin,
+			      timeout);
+
+	reinit_completion(&dsi->pll_stabilized);
 	samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
 
-	timeout = 3000;
-	do {
-		if (timeout-- == 0) {
-			dev_err(dsi->dev, "PLL failed to stabilize\n");
-			return 0;
-		}
-		if (driver_data->has_legacy_status_reg)
-			reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
-		else
-			reg = samsung_dsim_read(dsi, DSIM_LINK_STATUS_REG);
-	} while ((reg & BIT(driver_data->pll_stable_bit)) == 0);
+	if (wait_for_completion_timeout(&dsi->pll_stabilized,
+					usecs_to_jiffies(timeout))) {
+		dev_err(dsi->dev, "PLL failed to stabilize\n");
+		return 0;
+	}
 
 	dsi->hs_clock = fout;
 
@@ -1596,8 +1604,12 @@ static irqreturn_t samsung_dsim_irq(int irq, void *dev_id)
 		return IRQ_HANDLED;
 	}
 
-	if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
-			DSIM_INT_PLL_STABLE)))
+	if (status & DSIM_INT_PLL_STABLE) {
+		complete(&dsi->pll_stabilized);
+		return IRQ_HANDLED;
+	}
+
+	if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY)))
 		return IRQ_HANDLED;
 
 	if (samsung_dsim_transfer_finish(dsi))
@@ -2146,6 +2158,7 @@ int samsung_dsim_probe(struct platform_device *pdev)
 		return PTR_ERR(dsi);
 
 	init_completion(&dsi->completed);
+	init_completion(&dsi->pll_stabilized);
 	spin_lock_init(&dsi->transfer_lock);
 	INIT_LIST_HEAD(&dsi->transfer_list);
 
diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
index 03005e474704b..e3433da21ad08 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -123,6 +123,7 @@ struct samsung_dsim {
 	int state;
 	struct drm_property *brightness;
 	struct completion completed;
+	struct completion pll_stabilized;
 
 	spinlock_t transfer_lock; /* protects transfer_list */
 	struct list_head transfer_list;

-- 
2.53.0

Claude review: Fixes and enhancements for Exynos (7870) DSIM bridge driver

[Claude Code Review Bot]

Overall Series Review

Subject: Fixes and enhancements for Exynos (7870) DSIM bridge driver
Author: Kaustabh Chakraborty <kauschluss@disroot.org>
Patches: 3
Reviewed: 2026-03-25T08:14:56.487980

---

This is a 2-patch series fixing Exynos 7870 DSIM bridge driver issues. Patch 1 is a clean, well-motivated bug fix. **Patch 2 has a critical bug** — the `wait_for_completion_timeout()` return value check is inverted, meaning it will report failure on success and success on timeout. Additionally, the PLL_STABLE interrupt is masked after reset (line 1597-1602), so the interrupt will never fire in the first place.

---
Generated by Claude Code Patch Reviewer

Claude review: drm/bridge: samsung-dsim: enable MFLUSH_VS for Exynos 7870 DSIM

[Claude Code Review Bot]

Patch Review

**Verdict: Looks good.**

This is a straightforward fix. The MFLUSH_VS bit is active-high on Exynos 7870 (unlike other variants where it's active-low), so it needs to be explicitly set. The fix is correctly scoped inside the video mode block and only targets `DSIM_TYPE_EXYNOS7870`. It has a stable tag, a tested-by, and a downstream reference — all appropriate.

No issues found.

---

---
Generated by Claude Code Patch Reviewer

Claude review: drm/bridge: samsung-dsim: use DSIM interrupt to wait for PLL stability

[Claude Code Review Bot]

Patch Review

**Verdict: Has bugs that need fixing.**

**Bug 1 (Critical): Inverted `wait_for_completion_timeout` check**

At lines 868-871 of the patched file:

```c
if (wait_for_completion_timeout(&dsi->pll_stabilized,
                                usecs_to_jiffies(timeout))) {
    dev_err(dsi->dev, "PLL failed to stabilize\n");
    return 0;
}
```

`wait_for_completion_timeout()` returns **0 on timeout** and **>0 on success**. The condition is inverted — the error path runs on success, and the success path runs on timeout. This should be:

```c
if (!wait_for_completion_timeout(...)) {
```

**Bug 2 (Critical): PLL_STABLE interrupt is masked**

Looking at the interrupt handler at line 1596-1602, after `DSIM_INT_SW_RST_RELEASE`, the interrupt mask is set to block everything except `DSIM_INT_RX_DONE`, `DSIM_INT_SFR_FIFO_EMPTY`, `DSIM_INT_SFR_HDR_FIFO_EMPTY`, `DSIM_INT_RX_ECC_ERR`, and `DSIM_INT_SW_RST_RELEASE`. Notably, `DSIM_INT_PLL_STABLE` is **not** in this unmasked set — it remains masked. This means the PLL_STABLE interrupt will never be delivered after reset, and `wait_for_completion_timeout` will always time out.

The mask at line 1597 needs to also include `DSIM_INT_PLL_STABLE`:

```c
unsigned long mask = ~(DSIM_INT_RX_DONE |
                       DSIM_INT_SFR_FIFO_EMPTY |
                       DSIM_INT_SFR_HDR_FIFO_EMPTY |
                       DSIM_INT_RX_ECC_ERR |
                       DSIM_INT_SW_RST_RELEASE |
                       DSIM_INT_PLL_STABLE);
```

(Note: since bug 1 inverts the sense, on current hardware these two bugs may accidentally cancel out — the masked interrupt causes a timeout, which the inverted check treats as success. But that's fragile and wrong.)

**Minor: Typo in comment**

Line 855: `Calcutate` should be `Calculate`.

**Minor: Assumption about clk_data[0] being bus clock**

The comment says "It is assumed that the bus clock is the first clock in the provided bulk clock data." This holds for all current variants (exynos3 has `bus_clk`, exynos4 has `bus_clk`, exynos5433 has `bus_clk`, exynos7870 has `bus`), but for the IMX variants the first clock is also `bus_clk`. Still, this is fragile — if a future driver data entry reorders clocks, this silently breaks. Consider whether a named lookup would be more robust, though this is a minor concern.

**Minor: `usecs_to_jiffies` with small values**

With a typical HZ=250, `usecs_to_jiffies(100)` returns 1 jiffy (4ms), which is already much larger than 100µs. The "gracious lower bound of 100 microseconds" described in the commit message is somewhat misleading since the actual wait granularity is jiffies. This isn't a bug but worth being aware of.

---
Generated by Claude Code Patch Reviewer