From: Deborah Brouwer <deborah.brouwer@collabora.com>
To: dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org,
Boqun Feng <boqun@kernel.org>
Cc: Danilo Krummrich <dakr@kernel.org>,
Alice Ryhl <aliceryhl@google.com>,
Daniel Almeida <daniel.almeida@collabora.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Miguel Ojeda <ojeda@kernel.org>, Gary Guo <gary@garyguo.net>,
Björn Roy Baron <bjorn3_gh@protonmail.com>,
Benno Lossin <lossin@kernel.org>,
Andreas Hindborg <a.hindborg@kernel.org>,
Trevor Gross <tmgross@umich.edu>,
Steven Price <steven.price@arm.com>,
Boris Brezillon <boris.brezillon@collabora.com>,
Dirk Behme <dirk.behme@gmail.com>,
Alexandre Courbot <acourbot@nvidia.com>,
Deborah Brouwer <deborah.brouwer@collabora.com>,
Boqun Feng <boqun@kernel.org>
Subject: [PATCH v3 03/12] drm/tyr: Set interconnect coherency during probe
Date: Mon, 23 Mar 2026 17:18:05 -0700 [thread overview]
Message-ID: <20260323-b4-tyr-use-register-macro-v3-v3-3-a87daf9e4701@collabora.com> (raw)
In-Reply-To: <20260323-b4-tyr-use-register-macro-v3-v3-0-a87daf9e4701@collabora.com>
Currently GpuInfo reports the interconnect coherency protocol as none
without actually reading the `COHERENCY_ENABLE` register.
Although the result is the same, write `NO_COHERENCY` to the register
during probe and then read back the register to populate the GpuInfo
struct.
This ensures that GpuInfo is populated consistently and is always as
accurate as possible by reporting the register values directly.
Signed-off-by: Deborah Brouwer <deborah.brouwer@collabora.com>
---
drivers/gpu/drm/tyr/driver.rs | 5 +++++
drivers/gpu/drm/tyr/gpu.rs | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs
index 3ebb5e08bfca342f136e8d365b1d9dcb6cc3dbca..7232d9f9547c239689dc424380109a4e5140dd84 100644
--- a/drivers/gpu/drm/tyr/driver.rs
+++ b/drivers/gpu/drm/tyr/driver.rs
@@ -136,6 +136,11 @@ fn probe(
issue_soft_reset(pdev.as_ref(), &iomem)?;
gpu::l2_power_on(pdev.as_ref(), &iomem)?;
+ let io = (*iomem).access(pdev.as_ref())?;
+ // FIXME: This needs to be set properly once we get
+ // device_get_dma_attr() properly exposed to the rust drivers.
+ io.write_reg(COHERENCY_ENABLE::zeroed().with_l2_cache_protocol_select(CoherencyMode::None));
+
let gpu_info = GpuInfo::new(pdev.as_ref(), &iomem)?;
gpu_info_log(pdev.as_ref(), &iomem)?;
diff --git a/drivers/gpu/drm/tyr/gpu.rs b/drivers/gpu/drm/tyr/gpu.rs
index 4a50055b415c693a89cb99dba241b21351a14149..d5240f4567ca4e763b09e015908bdc5c22276e0d 100644
--- a/drivers/gpu/drm/tyr/gpu.rs
+++ b/drivers/gpu/drm/tyr/gpu.rs
@@ -60,7 +60,7 @@ pub(crate) fn new(dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<Self> {
io.read(TEXTURE_FEATURES::at(3)).supported_formats().get(),
],
as_present: io.read(AS_PRESENT).into_raw(),
- selected_coherency: uapi::drm_panthor_gpu_coherency_DRM_PANTHOR_GPU_COHERENCY_NONE,
+ selected_coherency: io.read(COHERENCY_ENABLE).into_raw(),
shader_present: io.read(SHADER_PRESENT).into_raw(),
l2_present: io.read(L2_PRESENT).into_raw(),
tiler_present: io.read(TILER_PRESENT).into_raw(),
--
2.52.0
next prev parent reply other threads:[~2026-03-24 0:18 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-24 0:18 [PATCH v3 00/12] drm/tyr: Use register! macro Deborah Brouwer
2026-03-24 0:18 ` [PATCH v3 01/12] drm/tyr: Use register! macro for GPU_CONTROL Deborah Brouwer
2026-03-24 9:56 ` Boris Brezillon
2026-03-24 11:23 ` Danilo Krummrich
2026-03-24 12:06 ` Boris Brezillon
2026-03-24 17:31 ` Danilo Krummrich
2026-03-24 18:15 ` Boris Brezillon
2026-03-24 19:03 ` Danilo Krummrich
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 02/12] drm/tyr: Print GPU_ID without filtering Deborah Brouwer
2026-03-24 9:54 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` Deborah Brouwer [this message]
2026-03-24 9:55 ` [PATCH v3 03/12] drm/tyr: Set interconnect coherency during probe Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 04/12] drm/tyr: Use register! macro for JOB_CONTROL Deborah Brouwer
2026-03-24 10:00 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 05/12] drm/tyr: Use register! macro for MMU_CONTROL Deborah Brouwer
2026-03-24 10:01 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 06/12] drm/tyr: Remove custom register struct Deborah Brouwer
2026-03-24 10:02 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 07/12] drm/tyr: Add MMU address space registers Deborah Brouwer
2026-03-24 10:03 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 08/12] drm/tyr: Add fields for MEMATTR register Deborah Brouwer
2026-03-24 10:05 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 09/12] drm/tyr: Add fields for COMMAND register Deborah Brouwer
2026-03-24 10:09 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 10/12] drm/tyr: Add fields for FAULTSTATUS register Deborah Brouwer
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 11/12] drm/tyr: Add fields for TRANSCFG register Deborah Brouwer
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 12/12] drm/tyr: Add DOORBELL_BLOCK registers Deborah Brouwer
2026-03-24 10:10 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 10:58 ` [PATCH v3 00/12] drm/tyr: Use register! macro Alice Ryhl
2026-03-24 12:35 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
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