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Mon, 23 Mar 2026 15:30:13 -0500 Received: from thonkpad (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Mon, 23 Mar 2026 15:30:12 -0500 From: To: , CC: , , , , , , Leo Li Subject: [PATCH v2 3/5] drm/amd/display: Refactor amdgpu_dm_crtc_set_vblank Date: Mon, 23 Mar 2026 16:27:53 -0400 Message-ID: <20260323202755.315929-4-sunpeng.li@amd.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260323202755.315929-1-sunpeng.li@amd.com> References: <20260323202755.315929-1-sunpeng.li@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004689:EE_|DM4PR12MB8523:EE_ X-MS-Office365-Filtering-Correlation-Id: 8e4d0bb6-ea41-4523-ba44-08de891afdd0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|36860700016|1800799024|56012099003|18002099003|22082099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mA2ChVgWV/nIbkuynPF/423XkGx7vepaA7I/QEUgUk1LqvD9R8wuec2FQSQN4KnYLkxuW0xf+YBy2hORiAxH+0qoixy4QYd+K1fzviHITOLI800eReZrb7Y8GH/7r1c/ExVt2ZbrleYNmdUqFObtHuV2w+EFNcvr0lnDG/pEOB+LJ14CXwclcP10jsRJPd+cWn9bLiJbri4SIda2Lf08K26t1ttpEKAzCZ5zIORO/IXNslpFblo5uHcmep8lkIwaOdbd2vkyefRsTYMayY87lJ7N+/K/3on8GA0Z8X5yhX/zBB1yGLy820f9363FkmglIRwzZph7jd0E24pqYSA+6430quRfQ+uRcANiWi/SyevstlacFxC6I5LRxVctbWxfoQOfts2F4XoMVnF+D26bLpQ6fKCgWLXhSB0urjPPEfwTBGs3VbxqV/1LBFCUpWtV X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2026 20:30:15.3257 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e4d0bb6-ea41-4523-ba44-08de891afdd0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004689.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8523 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Leo Li [Why] In preparation of implementing deferred vblank work, refactor amdgpu_dm_crtc_set_vblank to split out the actual enabling/disabling of vblank interrupts + restoring vblank counts/timestamps from the rest. [How] * Move the vblank_control_work init and queueing out into amdgpu_dm_crtc_queue_vblank_work() * Move crtc->enabled check out to parent function amdgpu_dm_crtc_enable_vblank() * Call amdgpu_dm_crtc_queue_vblank_work() from parent functions amdgpu_dm_crtc_(enable|disable)_vblank() * As a drive-by cleanup, make amdgpu_dm_crtc_(enable|disable)_vblank() static; they're not called from anywhere else. No functional changes are intended. Signed-off-by: Leo Li --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 87 +++++++++++++------ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.h | 4 - 2 files changed, 59 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 304437c2284d8..e6727d5098863 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -293,20 +293,12 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); struct amdgpu_display_manager *dm = &adev->dm; - struct vblank_control_work *work; int irq_type; int rc = 0; - if (enable && !acrtc->base.enabled) { - drm_dbg_vbl(crtc->dev, - "Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n", - acrtc->crtc_id, acrtc->base.enabled); - return -EINVAL; - } - irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); - if (enable) { + if (enable && crtc->enabled) { struct dc *dc = adev->dm.dc; struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; @@ -387,39 +379,78 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) return rc; } #endif + return 0; +} - if (amdgpu_in_reset(adev)) - return 0; - - if (dm->vblank_control_workqueue) { - work = kzalloc_obj(*work, GFP_ATOMIC); - if (!work) - return -ENOMEM; +static int amdgpu_dm_crtc_queue_vblank_work(struct amdgpu_display_manager *dm, + struct amdgpu_crtc *acrtc, + struct dm_crtc_state *acrtc_state, + bool enable) +{ + struct vblank_control_work *work; - INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker); - work->dm = dm; - work->acrtc = acrtc; - work->enable = enable; + work = kzalloc_obj(*work, GFP_ATOMIC); + if (!work) + return -ENOMEM; - if (acrtc_state->stream) { - dc_stream_retain(acrtc_state->stream); - work->stream = acrtc_state->stream; - } + INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker); + work->dm = dm; + work->acrtc = acrtc; + work->enable = enable; - queue_work(dm->vblank_control_workqueue, &work->work); + if (acrtc_state->stream) { + dc_stream_retain(acrtc_state->stream); + work->stream = acrtc_state->stream; } + queue_work(dm->vblank_control_workqueue, &work->work); return 0; } -int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc) +static int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc) { - return amdgpu_dm_crtc_set_vblank(crtc, true); + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); + struct amdgpu_device *adev = drm_to_adev(crtc->dev); + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + struct amdgpu_display_manager *dm = &adev->dm; + int ret; + + if (!crtc->enabled) { + drm_dbg_vbl(crtc->dev, + "Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n", + crtc->index, crtc->enabled); + return -EINVAL; + } + + ret = amdgpu_dm_crtc_set_vblank(crtc, true); + if (ret) + return ret; + + if (amdgpu_in_reset(adev)) + return 0; + + if (dm->vblank_control_workqueue) + return amdgpu_dm_crtc_queue_vblank_work(dm, acrtc, + acrtc_state, true); + + return 0; } -void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc) +static void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc) { + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); + struct amdgpu_device *adev = drm_to_adev(crtc->dev); + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + struct amdgpu_display_manager *dm = &adev->dm; + amdgpu_dm_crtc_set_vblank(crtc, false); + + if (amdgpu_in_reset(adev)) + return; + + if (dm->vblank_control_workqueue) + amdgpu_dm_crtc_queue_vblank_work(dm, acrtc, + acrtc_state, false); } static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h index c1212947a77b8..655a6c4f83fb8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h @@ -39,10 +39,6 @@ bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc); bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state); -int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc); - -void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc); - int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, struct drm_plane *plane, uint32_t link_index); -- 2.53.0