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From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
	Sean Paul <sean@poorly.run>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Dmitry Baryshkov <lumag@kernel.org>,
	Abhinav Kumar <abhinav.kumar@linux.dev>,
	Jessica Zhang <jesszhan0024@gmail.com>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Antonino Maniscalco <antomani103@gmail.com>,
	Connor Abbott <cwabbott0@gmail.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	Akhil P Oommen <akhilpo@oss.qualcomm.com>
Subject: [PATCH 04/16] drm/msm/a6xx: Add support for Debug HFI Q
Date: Tue, 24 Mar 2026 01:42:16 +0530	[thread overview]
Message-ID: <20260324-a8xx-gpu-batch2-v1-4-fc95b8d9c017@oss.qualcomm.com> (raw)
In-Reply-To: <20260324-a8xx-gpu-batch2-v1-0-fc95b8d9c017@oss.qualcomm.com>

Add the Debug HFI Queue which contains the F2H messages posted from the
GMU firmware. Having this data in coredump is useful to debug firmware
issues.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h       |  2 +-
 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c |  2 +-
 drivers/gpu/drm/msm/adreno/a6xx_hfi.c       | 16 +++++++++++++---
 drivers/gpu/drm/msm/adreno/a6xx_hfi.h       |  2 ++
 4 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
index 2af074c8e8cf..dd0614b19aac 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
@@ -110,7 +110,7 @@ struct a6xx_gmu {
 
 	unsigned long freq;
 
-	struct a6xx_hfi_queue queues[2];
+	struct a6xx_hfi_queue queues[HFI_MAX_QUEUES];
 
 	bool initialized;
 	bool hung;
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index d2d6b2fd3cba..018c164ad980 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -57,7 +57,7 @@ struct a6xx_gpu_state {
 	struct msm_gpu_state_bo *gmu_hfi;
 	struct msm_gpu_state_bo *gmu_debug;
 
-	s32 hfi_queue_history[2][HFI_HISTORY_SZ];
+	s32 hfi_queue_history[HFI_MAX_QUEUES][HFI_HISTORY_SZ];
 
 	struct list_head objs;
 
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index 53cfdf4e6c34..2daaa340366d 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
@@ -1056,8 +1056,8 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu)
 	struct a6xx_gmu_bo *hfi = &gmu->hfi;
 	struct a6xx_hfi_queue_table_header *table = hfi->virt;
 	struct a6xx_hfi_queue_header *headers = hfi->virt + sizeof(*table);
+	int table_size, idx;
 	u64 offset;
-	int table_size;
 
 	/*
 	 * The table size is the size of the table header plus all of the queue
@@ -1076,12 +1076,22 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu)
 	table->active_queues = ARRAY_SIZE(gmu->queues);
 
 	/* Command queue */
+	idx = 0;
 	offset = SZ_4K;
-	a6xx_hfi_queue_init(&gmu->queues[0], &headers[0], hfi->virt + offset,
+	a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
 		hfi->iova + offset, 0);
 
 	/* GMU response queue */
+	idx++;
 	offset += SZ_4K;
-	a6xx_hfi_queue_init(&gmu->queues[1], &headers[1], hfi->virt + offset,
+	a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
 		hfi->iova + offset, gmu->legacy ? 4 : 1);
+
+	/* GMU Debug queue */
+	idx++;
+	offset += SZ_4K;
+	a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
+		hfi->iova + offset, gmu->legacy ? 5 : 2);
+
+	WARN_ON(idx >= HFI_MAX_QUEUES);
 }
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
index 6f9f74a0bc85..19f6eca2c8c9 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
@@ -4,6 +4,8 @@
 #ifndef _A6XX_HFI_H_
 #define _A6XX_HFI_H_
 
+#define HFI_MAX_QUEUES 3
+
 struct a6xx_hfi_queue_table_header {
 	u32 version;
 	u32 size;		/* Size of the queue table in dwords */

-- 
2.51.0


  parent reply	other threads:[~2026-03-23 20:13 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-23 20:12 [PATCH 00/16] drm/msm: A8xx Support - Batch 2 Akhil P Oommen
2026-03-23 20:12 ` [PATCH 01/16] drm/msm/a8xx: Fix the ticks used in submit traces Akhil P Oommen
2026-03-24  9:48   ` Konrad Dybcio
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 02/16] drm/msm/a6xx: Switch to preemption safe AO counter Akhil P Oommen
2026-03-24  9:51   ` Konrad Dybcio
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 03/16] drm/msm/a6xx: Correct OOB usage Akhil P Oommen
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` Akhil P Oommen [this message]
2026-03-24 21:32   ` Claude review: drm/msm/a6xx: Add support for Debug HFI Q Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 05/16] drm/msm/adreno: Coredump on GPU/GMU init failures Akhil P Oommen
2026-03-24  9:53   ` Konrad Dybcio
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 06/16] drm/msm/a6xx: Use barriers while updating HFI Q headers Akhil P Oommen
2026-03-23 20:45   ` Rob Clark
2026-03-23 21:29     ` Dmitry Baryshkov
2026-03-23 21:35     ` Akhil P Oommen
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 07/16] drm/msm/a6xx: Use packed structs for HFI Akhil P Oommen
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 08/16] drm/msm/a6xx: Update HFI definitions Akhil P Oommen
2026-03-24 10:00   ` Konrad Dybcio
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 09/16] drm/msm/adreno: Implement gx_is_on() for A8x Akhil P Oommen
2026-03-24 10:03   ` Konrad Dybcio
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 10/16] drm/msm/a6xx: Fix gpu init from secure world Akhil P Oommen
2026-03-24 10:07   ` Konrad Dybcio
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 11/16] drm/msm/a8xx: Add SKU table for A840 Akhil P Oommen
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 12/16] drm/msm/a6xx: Add SKU detection support for X2-85 Akhil P Oommen
2026-03-23 20:37   ` Rob Clark
2026-03-23 21:34     ` Akhil P Oommen
2026-03-23 21:34   ` Dmitry Baryshkov
2026-03-24 10:09   ` Konrad Dybcio
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 13/16] drm/msm/a8xx: Implement IFPC support for A840 Akhil P Oommen
2026-03-24 10:13   ` Konrad Dybcio
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 14/16] drm/msm/a8xx: Preemption " Akhil P Oommen
2026-03-24 10:18   ` Konrad Dybcio
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 15/16] drm/msm/a6xx: Enable Preemption on X2-85 Akhil P Oommen
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 16/16] drm/msm/adreno: Expose a PARAM to check AQE support Akhil P Oommen
2026-03-23 21:36   ` Dmitry Baryshkov
2026-03-23 22:54     ` Connor Abbott
2026-03-24 10:19   ` Konrad Dybcio
2026-03-24 21:32   ` Claude review: " Claude Code Review Bot
2026-03-24 21:32 ` Claude review: drm/msm: A8xx Support - Batch 2 Claude Code Review Bot

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