From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23F1D105D990 for ; Wed, 8 Apr 2026 01:46:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6EC6310E504; Wed, 8 Apr 2026 01:46:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; secure) header.d=pm.me header.i=@pm.me header.b="Gf5Tbgap"; dkim-atps=neutral Received: from mail-10628.protonmail.ch (mail-10628.protonmail.ch [79.135.106.28]) by gabe.freedesktop.org (Postfix) with ESMTPS id D401010E504 for ; Wed, 8 Apr 2026 01:46:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775612768; x=1775871968; bh=Fuiz6jaa/oOGtjDuvFlJEcPtwK3etfMgKflUSlD5/z0=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=Gf5TbgapmSPX/O2TKhHXaNI57It0h7dcEpkEihFORRwDERuJkHQXfBGApH1wLCcBX F3fBbZLZ+QpQ9dmm9u9QOe/wqEq2lgKVA31U+IIWOvbM02r/bkcAOL7T9C/siac7mf zVBakXUsMUoAXJ1Rh23gthh6b4QTtqSZprCmfl31O6AS5bEfA1NP1MqKXCeCdW+mAa aO1TyT61/rH/jped2VHnyzeid5thmjq+u9UwkslwJGJhF1An3LoAaC86ccyMMif8o8 jPeVhzRj/BITtmUehvAzX4uW+0jCfeNzcwz7jek8XL6agFXT3DRz0V3CaC+4yYkk9I rUM8hWmWun2jA== Date: Wed, 08 Apr 2026 01:46:02 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Konrad Dybcio Subject: [PATCH RFC v3 5/7] drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature Message-ID: <20260407-adreno-810-v3-5-30cb7f196ed4@pm.me> In-Reply-To: <20260407-adreno-810-v3-0-30cb7f196ed4@pm.me> References: <20260407-adreno-810-v3-0-30cb7f196ed4@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 2e03c9d38f527f453c7f6cb36bea021f86045897 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" A8XX GPUs have two sets of protect registers: 64 global slots and 16 pipe specific slots. The last-span-unbound feature is only available on pipe protect registers, and should always target pipe slot 15. This matches the downstream driver which hardcodes pipe slot 15 for all A8XX GPUs (GRAPHICS.LA.15.0.r1) and resolves protect errors on A810. Reviewed-by: Konrad Dybcio Reviewed-by: Akhil P Oommen Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 1515ade22578..89a494bcea74 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -255,8 +255,8 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) =09 * Last span feature is only supported on PIPE specific register. =09 * So update those here =09 */ -=09a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_m= ax), final_cfg); -=09a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_m= ax), final_cfg); +=09a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); +=09a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); =20 =09a8xx_aperture_clear(gpu); } --=20 2.53.0