From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A756FD5F7D for ; Wed, 8 Apr 2026 05:40:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 995CF10E524; Wed, 8 Apr 2026 05:40:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="iCDoakT0"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 41CD210E524; Wed, 8 Apr 2026 05:40:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1775626825; x=1807162825; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Wjt88f970c17+tO51u8kpornq+2QQ/KEm0TI8mYHW5I=; b=iCDoakT0yFGY9P1fNgULxa+qsDJWzgiUtUXDzRxw9dKZYv641GG+sE+k vcrO+G4ZYKxBVaAyW5QZ/u+mQvl+ZW9joDak3/G1r9Afy7hVnpBcWlynW KauGJTqDpZl/aErhWiAzvyI8vjYtHNlrreWxsp8NwOAxmF8X9ktz8IinH weFKB5rEg3r9529za8y1Xvs6OGd089GTbcO1FwaGDikv5jng7mv+nZOw7 tf3XjXqnm0Smv2yFNQtFQrTYUyR1PjtcIIaNsZ2tHQjwyEpL3NlmRTv6l xCvgaRtCU5fiW4rl0hlR4OhqQD+stndHi5e1KBrN6ne3v7T1p9b1Ayruu Q==; X-CSE-ConnectionGUID: zIa0XJw4SoqcDPIhq70D3w== X-CSE-MsgGUID: iddULICCQGqdkI1Fc7er4Q== X-IronPort-AV: E=McAfee;i="6800,10657,11752"; a="80194904" X-IronPort-AV: E=Sophos;i="6.23,167,1770624000"; d="scan'208";a="80194904" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2026 22:40:25 -0700 X-CSE-ConnectionGUID: N6h+qcQcQAeN5KMpudGpAw== X-CSE-MsgGUID: 6G1TgPOXQIaO9EAZlCpZGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,167,1770624000"; d="scan'208";a="251518015" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa002.fm.intel.com with ESMTP; 07 Apr 2026 22:40:20 -0700 From: Chaitanya Kumar Borah To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: harry.wentland@amd.com, louis.chauvet@bootlin.com, mwen@igalia.com, contact@emersion.fr, alex.hung@amd.com, daniels@collabora.com, uma.shankar@intel.com, maarten.lankhorst@intel.com, pekka.paalanen@collabora.com, pranay.samala@intel.com, swati2.sharma@intel.com, chaitanya.kumar.borah@intel.com Subject: [PATCH v2 06/13] drm/i915/color: Extract HDR pre-CSC LUT programming to helper function Date: Wed, 8 Apr 2026 10:45:07 +0530 Message-Id: <20260408051514.608781-7-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260408051514.608781-1-chaitanya.kumar.borah@intel.com> References: <20260408051514.608781-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Pranay Samala As we prepare to add support for LUT programming in SDR planes, refactor HDR plane pre-CSC LUT programming to a helper. Signed-off-by: Pranay Samala Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_color.c | 92 ++++++++++++---------- 1 file changed, 51 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 6d1cffc6d2be..17ab4364faea 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3943,6 +3943,55 @@ xelpd_load_plane_csc_matrix(struct intel_dsb *dsb, ctm_to_twos_complement(input[11], 0, 12)); } +static void +xelpd_load_hdr_pre_csc_lut(struct intel_display *display, + struct intel_dsb *dsb, + enum pipe pipe, + enum plane_id plane, + const struct drm_color_lut32 *pre_csc_lut) +{ + u32 lut_size = 128; + u32 lut_val; + int i; + + intel_de_write_dsb(display, dsb, + PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), + PLANE_PAL_PREC_AUTO_INCREMENT); + + if (pre_csc_lut) { + for (i = 0; i < lut_size; i++) { + lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24); + + intel_de_write_dsb(display, dsb, + PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + lut_val); + } + + /* Program the max register to clamp values > 1.0. */ + /* TODO: Restrict to 0x7ffffff */ + do { + intel_de_write_dsb(display, dsb, + PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + (1 << 24)); + } while (i++ < 130); + } else { + for (i = 0; i < lut_size; i++) { + lut_val = (i * ((1 << 24) - 1)) / (lut_size - 1); + + intel_de_write_dsb(display, dsb, + PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), lut_val); + } + + do { + intel_de_write_dsb(display, dsb, + PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + 1 << 24); + } while (i++ < 130); + } + + intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); +} + static void xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb, const struct intel_plane_state *plane_state) @@ -3952,48 +4001,9 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb, enum pipe pipe = to_intel_plane(state->plane)->pipe; enum plane_id plane = to_intel_plane(state->plane)->id; const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data; - u32 i, lut_size; - if (icl_is_hdr_plane(display, plane)) { - lut_size = 128; - - intel_de_write_dsb(display, dsb, - PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), - PLANE_PAL_PREC_AUTO_INCREMENT); - - if (pre_csc_lut) { - for (i = 0; i < lut_size; i++) { - u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24); - - intel_de_write_dsb(display, dsb, - PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), - lut_val); - } - - /* Program the max register to clamp values > 1.0. */ - /* TODO: Restrict to 0x7ffffff */ - do { - intel_de_write_dsb(display, dsb, - PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), - (1 << 24)); - } while (i++ < 130); - } else { - for (i = 0; i < lut_size; i++) { - u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); - - intel_de_write_dsb(display, dsb, - PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v); - } - - do { - intel_de_write_dsb(display, dsb, - PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), - 1 << 24); - } while (i++ < 130); - } - - intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); - } + if (icl_is_hdr_plane(display, plane)) + xelpd_load_hdr_pre_csc_lut(display, dsb, pipe, plane, pre_csc_lut); } static void -- 2.25.1