From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CA1CFD5F9C for ; Wed, 8 Apr 2026 08:58:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 202F610E5DE; Wed, 8 Apr 2026 08:58:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ij+mB1+G"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0E62D10E5DD; Wed, 8 Apr 2026 08:58:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1775638701; x=1807174701; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w97To1uz79r0oCXBC62PCQxLVR6TuBW00cm+du3XD9M=; b=ij+mB1+Gp6KNY0rz0VspGU3HAivP6p1/djBLlZsfDyw76WnaLG4bhB1l y4avjAygHgFahwy3RlPCdnQ6BQEd3+/pN8xMDS+ZFdbfbSHiuoUlDCkJ+ wPndCUFmPKaJWWuyWTfAvvpWb4FG7CEnUn6UM94+IeflvTBiIGUH+/BNA gWE4L1Utop9eSmPgX9WuRlk2PqR+t2WTnV+HUHnfI8qC3ZbMZSnVTgb3A n24Uq7EPOwoXbUxVX6H9ajNGcDFATCUPoZC4mxzoc+0YIEeiTvqfuQNIG SKthWZdXiryau9Myb5SA0wTZ4feqMMQJKwvpgxHp4mMMi6hgSkMCBYwm+ w==; X-CSE-ConnectionGUID: XoTm8/rNQc6bLNW4WYgXzA== X-CSE-MsgGUID: fbX4BC6DQdiHX5Ud8daclA== X-IronPort-AV: E=McAfee;i="6800,10657,11752"; a="76516680" X-IronPort-AV: E=Sophos;i="6.23,167,1770624000"; d="scan'208";a="76516680" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2026 01:58:21 -0700 X-CSE-ConnectionGUID: dmY1aBKiSpOJqsKKzU01JA== X-CSE-MsgGUID: wqrO+3c9S3i3sBwlxhGArQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,167,1770624000"; d="scan'208";a="227572599" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2026 01:58:19 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, jouni.hogander@intel.com, animesh.manna@intel.com, Ankit Nautiyal Subject: [PATCH 17/26] drm/i915/dp: Add member to intel_dp to store AS SDP v2 support Date: Wed, 8 Apr 2026 14:12:29 +0530 Message-ID: <20260408084239.1295325-18-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260408084239.1295325-1-ankit.k.nautiyal@intel.com> References: <20260408084239.1295325-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" eDP v1.5a advertises support for Adaptive Sync SDP and with that the support for AS SDP v2 is mandatory. DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD 0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP version 2 (AS SDP v2), which allows the source to set the version in HB2[4:0] and the payload length in HB3[5:0] of the AS SDP header. DP v2.1 SCR also introduces ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR in the Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is set, the sink does not support asynchronous video timing while in a Panel Replay Active state and the source is required to keep transmitting Adaptive-Sync SDPs. The spec mandates that such sinks shall support AS SDP v2. Infer AS SDP v2 support from these capabilities and store it in struct intel_dp for use by subsequent feature enablement changes. v2: - Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to determine AS SDP v2 support. (Ville) v3: - Use helper to determine asynch video timing support. v4: - Add AS SDP v2 support for eDP as per v1.5a. - Add a check for Panel Replay support before checking for Async video timing support in PR - Add a TODO for Display ID and PCON considerations. (Ville) Signed-off-by: Ankit Nautiyal --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 49 +++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e2496db1642a..efc609eef4f5 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1870,6 +1870,7 @@ struct intel_dp { /* connector directly attached - won't be use for modeset in mst world */ struct intel_connector *attached_connector; bool as_sdp_supported; + bool as_sdp_v2_supported; struct drm_dp_tunnel *tunnel; bool tunnel_suspended:1; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index bca5dc2c3b30..aa035cb2fcc5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6307,6 +6307,46 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) false); } +static bool +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp) +{ + u8 rx_features; + + /* + * The DP spec does not explicitly provide the AS SDP v2 capability. + * So based on the DP v2.1 SCR, we infer it from the following bits: + * + * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates support for + * FAVT, which is explicitly defined to use AS SDP v2. + * + * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR indicates that the sink + * does not support asynchronous video timing while in PR Active, + * requiring the source to keep transmitting Adaptive-Sync SDPs. The + * spec mandates that such sinks shall support AS SDP v2. + * + * #TODO: Check the Adaptive-Sync DisplayID 2.1 block once DisplayID + * parsing is available. This may help detect AS SDP v2 support for + * native DP 2.1 sinks that do not expose FAVT or PR-based capability + * bits. + * + * In the presence of PCONs, check PCON support from DPCD and sink + * support from Display ID. + */ + + if (drm_dp_dpcd_read_byte(&intel_dp->aux, + DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1, + &rx_features) == 1) { + if (rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED) + return true; + } + + if (intel_dp->psr.sink_panel_replay_support && + !intel_psr_pr_async_video_timing_supported(intel_dp)) + return true; + + return false; +} + static void intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) { @@ -6314,6 +6354,15 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) intel_dp->as_sdp_supported = HAS_AS_SDP(display) && drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); + + if (!intel_dp->as_sdp_supported) + return; + + /* eDP Adaptive-Sync SDP always uses AS SDP v2 */ + if (intel_dp_is_edp(intel_dp)) + intel_dp->as_sdp_v2_supported = true; + else + intel_dp->as_sdp_v2_supported = intel_dp_sink_supports_as_sdp_v2(intel_dp); } static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external) -- 2.45.2