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Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C714.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB10378 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a GPU_CONTROL-local iomem pointer to struct panthor_gpu and use it for GPU register accesses. This limits GPU register accesses to the GPU block instead of using the device-wide MMIO mapping directly. Interrupt register accesses continue to use the IRQ-local base provided by the common IRQ helpers. This is a refactoring only and does not change behaviour. Signed-off-by: Karunika Choo --- drivers/gpu/drm/panthor/panthor_gpu.c | 61 +++++++++++++--------- drivers/gpu/drm/panthor/panthor_gpu_regs.h | 6 +-- 2 files changed, 38 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c index 3ddce35ed8b5..abd94de5d15d 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -29,6 +29,9 @@ * struct panthor_gpu - GPU block management data. */ struct panthor_gpu { + /** @iomem: CPU mapping of GPU_CONTROL iomem region */ + void __iomem *iomem; + /** @irq: GPU irq. */ struct panthor_irq irq; @@ -56,12 +59,13 @@ struct panthor_gpu { static void panthor_gpu_coherency_set(struct panthor_device *ptdev) { - gpu_write(ptdev->iomem, GPU_COHERENCY_PROTOCOL, + gpu_write(ptdev->gpu->iomem, GPU_COHERENCY_PROTOCOL, ptdev->gpu_info.selected_coherency); } static void panthor_gpu_l2_config_set(struct panthor_device *ptdev) { + struct panthor_gpu *gpu = ptdev->gpu; const struct panthor_soc_data *data = ptdev->soc_data; u32 l2_config; u32 i; @@ -75,26 +79,28 @@ static void panthor_gpu_l2_config_set(struct panthor_device *ptdev) } for (i = 0; i < ARRAY_SIZE(data->asn_hash); i++) - gpu_write(ptdev->iomem, GPU_ASN_HASH(i), data->asn_hash[i]); + gpu_write(gpu->iomem, GPU_ASN_HASH(i), data->asn_hash[i]); - l2_config = gpu_read(ptdev->iomem, GPU_L2_CONFIG); + l2_config = gpu_read(gpu->iomem, GPU_L2_CONFIG); l2_config |= GPU_L2_CONFIG_ASN_HASH_ENABLE; - gpu_write(ptdev->iomem, GPU_L2_CONFIG, l2_config); + gpu_write(gpu->iomem, GPU_L2_CONFIG, l2_config); } static void panthor_gpu_irq_handler(struct panthor_device *ptdev, u32 status) { - gpu_write(ptdev->iomem, GPU_INT_CLEAR, status); + struct panthor_gpu *gpu = ptdev->gpu; + + gpu_write(gpu->irq.iomem, INT_CLEAR, status); if (tracepoint_enabled(gpu_power_status) && (status & GPU_POWER_INTERRUPTS_MASK)) trace_gpu_power_status(ptdev->base.dev, - gpu_read64(ptdev->iomem, SHADER_READY), - gpu_read64(ptdev->iomem, TILER_READY), - gpu_read64(ptdev->iomem, L2_READY)); + gpu_read64(gpu->iomem, SHADER_READY), + gpu_read64(gpu->iomem, TILER_READY), + gpu_read64(gpu->iomem, L2_READY)); if (status & GPU_IRQ_FAULT) { - u32 fault_status = gpu_read(ptdev->iomem, GPU_FAULT_STATUS); - u64 address = gpu_read64(ptdev->iomem, GPU_FAULT_ADDR); + u32 fault_status = gpu_read(gpu->iomem, GPU_FAULT_STATUS); + u64 address = gpu_read64(gpu->iomem, GPU_FAULT_ADDR); drm_warn(&ptdev->base, "GPU Fault 0x%08x (%s) at 0x%016llx\n", fault_status, panthor_exception_name(ptdev, fault_status & 0xFF), @@ -147,6 +153,7 @@ int panthor_gpu_init(struct panthor_device *ptdev) if (!gpu) return -ENOMEM; + gpu->iomem = ptdev->iomem + GPU_CONTROL_BASE; spin_lock_init(&gpu->reqs_lock); init_waitqueue_head(&gpu->reqs_acked); mutex_init(&gpu->cache_flush_lock); @@ -202,10 +209,11 @@ int panthor_gpu_block_power_off(struct panthor_device *ptdev, u32 pwroff_reg, u32 pwrtrans_reg, u64 mask, u32 timeout_us) { + struct panthor_gpu *gpu = ptdev->gpu; u32 val; int ret; - ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val, + ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, pwrtrans_reg, val, !(mask & val), 100, timeout_us); if (ret) { drm_err(&ptdev->base, @@ -214,9 +222,9 @@ int panthor_gpu_block_power_off(struct panthor_device *ptdev, return ret; } - gpu_write64(ptdev->iomem, pwroff_reg, mask); + gpu_write64(gpu->iomem, pwroff_reg, mask); - ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val, + ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, pwrtrans_reg, val, !(mask & val), 100, timeout_us); if (ret) { drm_err(&ptdev->base, @@ -245,10 +253,11 @@ int panthor_gpu_block_power_on(struct panthor_device *ptdev, u32 pwron_reg, u32 pwrtrans_reg, u32 rdy_reg, u64 mask, u32 timeout_us) { + struct panthor_gpu *gpu = ptdev->gpu; u32 val; int ret; - ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val, + ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, pwrtrans_reg, val, !(mask & val), 100, timeout_us); if (ret) { drm_err(&ptdev->base, @@ -257,9 +266,9 @@ int panthor_gpu_block_power_on(struct panthor_device *ptdev, return ret; } - gpu_write64(ptdev->iomem, pwron_reg, mask); + gpu_write64(gpu->iomem, pwron_reg, mask); - ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, rdy_reg, val, + ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, rdy_reg, val, (mask & val) == val, 100, timeout_us); if (ret) { @@ -318,6 +327,7 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptdev) int panthor_gpu_flush_caches(struct panthor_device *ptdev, u32 l2, u32 lsc, u32 other) { + struct panthor_gpu *gpu = ptdev->gpu; unsigned long flags; int ret = 0; @@ -327,7 +337,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev, spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); if (!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) { ptdev->gpu->pending_reqs |= GPU_IRQ_CLEAN_CACHES_COMPLETED; - gpu_write(ptdev->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); + gpu_write(gpu->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); } else { ret = -EIO; } @@ -341,7 +351,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev, msecs_to_jiffies(100))) { spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 && - !(gpu_read(ptdev->iomem, GPU_INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED)) + !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED)) ret = -ETIMEDOUT; else ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED; @@ -364,6 +374,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev, */ int panthor_gpu_soft_reset(struct panthor_device *ptdev) { + struct panthor_gpu *gpu = ptdev->gpu; bool timedout = false; unsigned long flags; @@ -371,8 +382,8 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev) if (!drm_WARN_ON(&ptdev->base, ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED)) { ptdev->gpu->pending_reqs |= GPU_IRQ_RESET_COMPLETED; - gpu_write(ptdev->iomem, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); - gpu_write(ptdev->iomem, GPU_CMD, GPU_SOFT_RESET); + gpu_write(gpu->irq.iomem, INT_CLEAR, GPU_IRQ_RESET_COMPLETED); + gpu_write(gpu->iomem, GPU_CMD, GPU_SOFT_RESET); } spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags); @@ -381,7 +392,7 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev) msecs_to_jiffies(100))) { spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); if ((ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED) != 0 && - !(gpu_read(ptdev->iomem, GPU_INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED)) + !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED)) timedout = true; else ptdev->gpu->pending_reqs &= ~GPU_IRQ_RESET_COMPLETED; @@ -430,17 +441,17 @@ void panthor_gpu_resume(struct panthor_device *ptdev) u64 panthor_gpu_get_timestap(struct panthor_device *ptdev) { - return gpu_read64_counter(ptdev->iomem, GPU_TIMESTAMP); + return gpu_read64_counter(ptdev->gpu->iomem, GPU_TIMESTAMP); } u64 panthor_gpu_get_timestap_offset(struct panthor_device *ptdev) { - return gpu_read64(ptdev->iomem, GPU_TIMESTAMP_OFFSET); + return gpu_read64(ptdev->gpu->iomem, GPU_TIMESTAMP_OFFSET); } u64 panthor_gpu_get_cycle_count(struct panthor_device *ptdev) { - return gpu_read64_counter(ptdev->iomem, GPU_CYCLE_COUNT); + return gpu_read64_counter(ptdev->gpu->iomem, GPU_CYCLE_COUNT); } int panthor_gpu_coherency_init(struct panthor_device *ptdev) @@ -459,7 +470,7 @@ int panthor_gpu_coherency_init(struct panthor_device *ptdev) /* Check if the ACE-Lite coherency protocol is actually supported by the GPU. * ACE protocol has never been supported for command stream frontend GPUs. */ - if ((gpu_read(ptdev->iomem, GPU_COHERENCY_FEATURES) & + if ((gpu_read(ptdev->gpu->iomem, GPU_COHERENCY_FEATURES) & GPU_COHERENCY_PROT_BIT(ACE_LITE))) { ptdev->gpu_info.selected_coherency = GPU_COHERENCY_ACE_LITE; return 0; diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h index d7cf5165e987..f64e7661f765 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu_regs.h +++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h @@ -4,6 +4,8 @@ #ifndef __PANTHOR_GPU_REGS_H__ #define __PANTHOR_GPU_REGS_H__ +#define GPU_CONTROL_BASE 0x0 + #define GPU_L2_FEATURES 0x4 #define GPU_L2_FEATURES_LINE_SIZE(x) (1 << ((x) & GENMASK(7, 0))) @@ -20,10 +22,6 @@ #define GPU_CSF_ID 0x1C #define GPU_INT_BASE 0x20 -#define GPU_INT_RAWSTAT 0x20 -#define GPU_INT_CLEAR 0x24 -#define GPU_INT_MASK 0x28 -#define GPU_INT_STAT 0x2c #define GPU_IRQ_FAULT BIT(0) #define GPU_IRQ_PROTM_FAULT BIT(1) #define GPU_IRQ_RESET_COMPLETED BIT(8) -- 2.43.0