From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 767DDFF886D for ; Wed, 29 Apr 2026 09:39:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1869C10EF0E; Wed, 29 Apr 2026 09:39:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=collabora.com header.i=@collabora.com header.b="TSfG2n2H"; dkim-atps=neutral Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) by gabe.freedesktop.org (Postfix) with ESMTPS id 11E8610EEFE for ; Wed, 29 Apr 2026 09:38:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1777455535; bh=JCuOHv6q4CvfrEuovqS12pygdtTMQTEp7KamPRltOjE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TSfG2n2HjQ4rtF2RwJBOR9ZOxbfP4p3OD7fG9WQBR4/OT7agh+IRG9A8DaH8sIN8y Vo3q6Q1skqDIQ1krZSQbWoT5ZEXD9hr3SJdp82eS/9LOtD6Hg0IZOF20aTmuC2mno3 AOLIejMI4aaiQZ7fMvuV+uXeJ1FpayIGWVXWFDvLHtyLCsxFoYDgANbVtD5R21S+ie aR/khir+qpiShjvasH+9G+Q8SQwUMWRTQT1GTgDe7D3P5PgAAk45yVNJs9e0Szwo9t wouPtDPOHl6AGGbIDfPHqGFKmdsCMhOHRcrDb+E+0BpSiTDNLZZoTt/M5TX2SAO7Bn ajciO5cjeG5qQ== Received: from [100.64.0.11] (unknown [100.64.0.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id 6B0E717E1513; Wed, 29 Apr 2026 11:38:55 +0200 (CEST) From: Boris Brezillon Date: Wed, 29 Apr 2026 11:38:29 +0200 Subject: [PATCH 02/10] drm/panthor: Move the register accessors before the IRQ helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260429-panthor-signal-from-irq-v1-2-4b92ae4142d2@collabora.com> References: <20260429-panthor-signal-from-irq-v1-0-4b92ae4142d2@collabora.com> In-Reply-To: <20260429-panthor-signal-from-irq-v1-0-4b92ae4142d2@collabora.com> To: Steven Price , Liviu Dudau Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Boris Brezillon X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777455534; l=5600; i=boris.brezillon@collabora.com; s=20260429; h=from:subject:message-id; bh=JCuOHv6q4CvfrEuovqS12pygdtTMQTEp7KamPRltOjE=; b=5KZWvVTmvzOp3oomDi6MJLECzWK3GWbrrnHtLeoY3NVLgSNPD6m85pLKkTE88DUF0Cx691Hn6 2LPA6D2gU9sDxE2qhBUg4m79aMS2v8410z4ihh9NyH01xzI1HqHMzRt X-Developer-Key: i=boris.brezillon@collabora.com; a=ed25519; pk=eN+ORdOgQY7d5U+0kA8h5bf67XdD8bhKbjD/TCHexSY= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" We're about to add an IRQ inline helper using gpu_read(). Move things around to avoid forward declarations. No functional changes. Signed-off-by: Boris Brezillon --- drivers/gpu/drm/panthor/panthor_device.h | 142 +++++++++++++++---------------- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h index 3f91ba73829d..768fc1992368 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -495,6 +495,77 @@ panthor_exception_is_fault(u32 exception_code) const char *panthor_exception_name(struct panthor_device *ptdev, u32 exception_code); +static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data) +{ + writel(data, iomem + reg); +} + +static inline u32 gpu_read(void __iomem *iomem, u32 reg) +{ + return readl(iomem + reg); +} + +static inline u32 gpu_read_relaxed(void __iomem *iomem, u32 reg) +{ + return readl_relaxed(iomem + reg); +} + +static inline void gpu_write64(void __iomem *iomem, u32 reg, u64 data) +{ + gpu_write(iomem, reg, lower_32_bits(data)); + gpu_write(iomem, reg + 4, upper_32_bits(data)); +} + +static inline u64 gpu_read64(void __iomem *iomem, u32 reg) +{ + return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32)); +} + +static inline u64 gpu_read64_relaxed(void __iomem *iomem, u32 reg) +{ + return (gpu_read_relaxed(iomem, reg) | + ((u64)gpu_read_relaxed(iomem, reg + 4) << 32)); +} + +static inline u64 gpu_read64_counter(void __iomem *iomem, u32 reg) +{ + u32 lo, hi1, hi2; + do { + hi1 = gpu_read(iomem, reg + 4); + lo = gpu_read(iomem, reg); + hi2 = gpu_read(iomem, reg + 4); + } while (hi1 != hi2); + return lo | ((u64)hi2 << 32); +} + +#define gpu_read_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ + read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false, \ + iomem, reg) + +#define gpu_read_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ + timeout_us) \ + read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us, \ + false, iomem, reg) + +#define gpu_read64_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ + read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false, \ + iomem, reg) + +#define gpu_read64_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ + timeout_us) \ + read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us, \ + false, iomem, reg) + +#define gpu_read_relaxed_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ + timeout_us) \ + read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us, \ + timeout_us, false, iomem, reg) + +#define gpu_read64_relaxed_poll_timeout(iomem, reg, val, cond, delay_us, \ + timeout_us) \ + read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us, \ + false, iomem, reg) + #define INT_RAWSTAT 0x0 #define INT_CLEAR 0x4 #define INT_MASK 0x8 @@ -629,75 +700,4 @@ static inline void panthor_ ## __name ## _irq_disable_events(struct panthor_irq extern struct workqueue_struct *panthor_cleanup_wq; -static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data) -{ - writel(data, iomem + reg); -} - -static inline u32 gpu_read(void __iomem *iomem, u32 reg) -{ - return readl(iomem + reg); -} - -static inline u32 gpu_read_relaxed(void __iomem *iomem, u32 reg) -{ - return readl_relaxed(iomem + reg); -} - -static inline void gpu_write64(void __iomem *iomem, u32 reg, u64 data) -{ - gpu_write(iomem, reg, lower_32_bits(data)); - gpu_write(iomem, reg + 4, upper_32_bits(data)); -} - -static inline u64 gpu_read64(void __iomem *iomem, u32 reg) -{ - return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32)); -} - -static inline u64 gpu_read64_relaxed(void __iomem *iomem, u32 reg) -{ - return (gpu_read_relaxed(iomem, reg) | - ((u64)gpu_read_relaxed(iomem, reg + 4) << 32)); -} - -static inline u64 gpu_read64_counter(void __iomem *iomem, u32 reg) -{ - u32 lo, hi1, hi2; - do { - hi1 = gpu_read(iomem, reg + 4); - lo = gpu_read(iomem, reg); - hi2 = gpu_read(iomem, reg + 4); - } while (hi1 != hi2); - return lo | ((u64)hi2 << 32); -} - -#define gpu_read_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ - read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false, \ - iomem, reg) - -#define gpu_read_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ - timeout_us) \ - read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us, \ - false, iomem, reg) - -#define gpu_read64_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ - read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false, \ - iomem, reg) - -#define gpu_read64_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ - timeout_us) \ - read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us, \ - false, iomem, reg) - -#define gpu_read_relaxed_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ - timeout_us) \ - read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us, \ - timeout_us, false, iomem, reg) - -#define gpu_read64_relaxed_poll_timeout(iomem, reg, val, cond, delay_us, \ - timeout_us) \ - read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us, \ - false, iomem, reg) - #endif -- 2.53.0