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Ip=[212.61.153.67]; Helo=[webmail.prodrive.nl] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D09.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU4PR02MB12227 X-Mailman-Approved-At: Thu, 30 Apr 2026 17:06:40 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Some MIPI DSI encoder drivers, like the Samsung DSI controller found in i.MX8M Mini, enable the DSI clock on encoder enable. The sn65dsi83 pre_enable is executed before the DSIM encoder enable. As the DSI input clock is the PLL input clock, the PLL cannot be locked in pre_enable. Enable and lock the PLL in enable instead of pre_enable, to make sure the input clock is available. Fixes: dd9e329af723 ("drm/bridge: ti-sn65dsi83: Fix enable/disable flow to meet spec") Signed-off-by: Paul Geurts --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 35 +++++++++++++-------------- 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c index 17a885244e1e..018e524c473c 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -525,7 +525,6 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, struct drm_crtc *crtc; bool lvds_format_24bpp; bool lvds_format_jeida; - unsigned int pval; __le16 le16val; u16 val; int ret; @@ -670,6 +669,21 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, mode->vsync_start - mode->vdisplay); regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); + devm_add_action(ctx->dev, sn65dsi83_release_resources, ctx); +err_exit: + drm_bridge_exit(idx); +} + +static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); + unsigned int pval; + int idx, ret; + + if (!drm_bridge_enter(bridge, &idx)) + return; + /* Enable PLL */ regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); usleep_range(3000, 4000); @@ -680,7 +694,7 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); /* On failure, disable PLL again and exit. */ regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); - goto err_add_action; + goto out; } /* Trigger reset after CSR register update. */ @@ -689,22 +703,6 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, /* Wait for 10ms after soft reset as specified in datasheet */ usleep_range(10000, 12000); -err_add_action: - devm_add_action(ctx->dev, sn65dsi83_release_resources, ctx); -err_exit: - drm_bridge_exit(idx); -} - -static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) -{ - struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); - unsigned int pval; - int idx; - - if (!drm_bridge_enter(bridge, &idx)) - return; - /* Clear all errors that got asserted during initialization. */ regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); regmap_write(ctx->regmap, REG_IRQ_STAT, pval); @@ -724,6 +722,7 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, sn65dsi83_monitor_start(ctx); } +out: drm_bridge_exit(idx); } -- 2.39.2