From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D25B7CD3426 for ; Fri, 1 May 2026 07:15:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C63BC10E514; Fri, 1 May 2026 07:15:44 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=fairphone.com header.i=@fairphone.com header.b="RIJwXlDO"; dkim-atps=neutral Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by gabe.freedesktop.org (Postfix) with ESMTPS id B12E810E6DA for ; Fri, 1 May 2026 07:15:43 +0000 (UTC) Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4891f625344so18176675e9.0 for ; Fri, 01 May 2026 00:15:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1777619741; x=1778224541; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=o5V6knZIhB7/WOjEgsyLqxPXBwOa+O33dpe+cxcVxdw=; b=RIJwXlDOSGF5NO6+pR5lGc+BDbr7bGPBLX+B9v8KJuYdZXxe43csFWH+ZHZ/ZL2tSw tTpXehRV2a6osm1fh4J8AAkSz51MhFHs9jlC93/HPq1PKOf1LmWIBUV945htjWJKDBFO X8hzCYxwt+M/p0q0OiNczXjVPvmmZqEoi12i2XobXH8fzi1hTrlIYUzmsxIndGLRFSEp VJMDtgdz+fPHKdLcIaAN2aUuBG4S9t8eV/GL7sp/wYIzSalnLj1q0N+IsyW1VmTVS8lT WKMGQ4W6XVi1gIef0Nk1+gfojuf0rZkZA5oN/Dp2Q83vs2Qo3bYh9oW7C/0hseJp/FX8 EmLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777619741; x=1778224541; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=o5V6knZIhB7/WOjEgsyLqxPXBwOa+O33dpe+cxcVxdw=; b=WdktB4sKsWq6eyi7zGXUdrhj/Ej/S0UWLMU7M54udxXaWV4rLhQzrmy7qvK4VFJwZn 9V3A7Cgj90gCg2bUNPeAPsMaA4A3chHjVGUwG4pFG46hEZKx44UgjMRP4kX5wL2+5guE 1h/cOaiLcTjKXB9mUIUXqagyUuZc5BORc0GYXXnwwdccYM+t/aH6d2Bn10oxBgr+buMh y0pwOkxDvkuYFghLwEgZOoVDoUBpNCRm3G7TNBPYS07mf+6g6hp7yufdyhLWGeAWqCG8 4ljJpdFf8FPnNNPTV3WfpTCLjWNeVdVRie8bL6eGR+6U16rQX9NJ8DDnr3NARr+awhgT LHrg== X-Forwarded-Encrypted: i=1; AFNElJ/AkCD+6ILQV1Fob6xoJnDDyjE0qq7Jmk4/DgRuFWG6GDrJmC+Dd484KFIw+HqcWu8DEiyKwqrd9ZA=@lists.freedesktop.org X-Gm-Message-State: AOJu0Yxt0jCyLXvTimzb8TM1c5lrlN9hp2lFxeVKHHhWC2lN7pSmxnue QmORn2iz0h5aroG5zzQOF/zkiIrFHNEE2aJ2ssWFbU1NzrTUozFJB9LElidyPjjIeSM= X-Gm-Gg: AeBDietcvu5BsVO53EAAgFmT4p2UjnoCEUbrkMTYYy09IeTa3aNDpW86fmrKZPvCh2d KQMYSnE+G0J2pn7gqbs6oDxnoC10Hzt5+BRaCpInycyXRN3p05Jr2701xhTET/Kev+p2S5Qh9+X +knwdDxU6JPkXqH35qTm1hRy6ytw2C1lFNmnu1RzZA0ev0yQUW8OQoHnJqMnIGvGMva9t+uskdg Fdl2dwod20XF821UFHP9OmlUc2k6Bft7BIyj0kq1NuzfplbeSPHpTQIvs1ahXOzGO6yw2KtNoJ9 UsIrEDWP8yR2F8/FS35nFJ6YMC1muCBHsgoSioXEGaj2tlDDftZTQK0GyQUMy13dmwxnEqp9G8N C+YXUC7bxjM7DMdUY6UVUhKVmAWc/eAsgiVk0Gf1SgPa4POgE5EJpk/S/ruefnWTGLMum94Y2PS kQ6/Ok1fN0MFIxLJipht3M86/DLHbgT4oynATjawjLqkOXt22AZEBw20HzIMVF4WajVMendHA/y /1pPn6p X-Received: by 2002:a05:600c:8707:b0:489:1baf:8c03 with SMTP id 5b1f17b1804b1-48a86084573mr100270135e9.11.1777619741165; Fri, 01 May 2026 00:15:41 -0700 (PDT) Received: from [192.168.178.36] (046124199213.public.t-mobile.at. [46.124.199.213]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a8eba8487sm29668085e9.11.2026.05.01.00.15.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 May 2026 00:15:40 -0700 (PDT) From: Luca Weiss Date: Fri, 01 May 2026 09:14:51 +0200 Subject: [PATCH v3 9/9] arm64: dts: qcom: milos: Add display (MDSS) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260501-milos-mdss-v3-9-58bfc58c0e13@fairphone.com> References: <20260501-milos-mdss-v3-0-58bfc58c0e13@fairphone.com> In-Reply-To: <20260501-milos-mdss-v3-0-58bfc58c0e13@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Marek , Krishna Manikandan , Neil Armstrong , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss , Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777619720; l=6617; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=ObeaTI9oGiLe42YJXwSvm93zhEz3BDcXzX0FYlJcloY=; b=zj1t8gQVCHYk3oC6SAPsn7UO6RJgw4YGPsdhnB/J6RQCEAF3yS3JGy0esTz0d8UzNpzwjw6y9 /8Tr3iiNnzrB7vU0rwmU1M7pWpceKfc99fqrABHozUciNc0mu9Oc+Qv X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add device nodes for display: MDSS, DPU, DSI and DSI PHY. DisplayPort is not added for now. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/milos.dtsi | 211 +++++++++++++++++++++++++++++++++++- 1 file changed, 209 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 4a64a98a434b..1a9b72d61688 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2025, Luca Weiss */ +#include #include #include #include @@ -1928,6 +1929,212 @@ camcc: clock-controller@adb0000 { #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,milos-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,milos-dpu"; + reg = <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-402000000 { + opp-hz = /bits/ 64 <402000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-535000000 { + opp-hz = /bits/ 64 <535000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae94000 0x0 0x1000>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,milos-dsi-phy-4nm"; + reg = <0x0 0x0ae95000 0x0 0x200>, + <0x0 0x0ae95200 0x0 0x300>, + <0x0 0x0ae95500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,milos-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; @@ -1936,8 +2143,8 @@ dispcc: clock-controller@af00000 { <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <0>, /* dsi0_phy_pll_out_byteclk */ - <0>, /* dsi0_phy_pll_out_dsiclk */ + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, /* dp0_phy_pll_link_clk */ <0>; /* dp0_phy_pll_vco_div_clk */ -- 2.54.0