From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBBFFCD3439 for ; Tue, 5 May 2026 07:12:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 67E1B10E980; Tue, 5 May 2026 07:12:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; secure) header.d=usp.br header.i=@usp.br header.b="n+iIhMwk"; dkim-atps=neutral Received: from mail-dl1-f42.google.com (mail-dl1-f42.google.com [74.125.82.42]) by gabe.freedesktop.org (Postfix) with ESMTPS id 055FC10E8FF for ; Tue, 5 May 2026 02:14:35 +0000 (UTC) Received: by mail-dl1-f42.google.com with SMTP id a92af1059eb24-12c88e5f4aeso2757775c88.0 for ; Mon, 04 May 2026 19:14:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=usp.br; s=usp-google; t=1777947275; x=1778552075; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DgBBX+Spc3GcSsocR+N3z63BxmLpev0+iIDdKrva0dY=; b=n+iIhMwkR+m2r420PWPypyYeJlW9OuXGToFZpDNq9AeJsipTMCLu7twt/5NDH0SFHU A4URVJorC+balU1L5pv/crpIzYkhwbPFowge44gZPG2akVq84crjzCGz7qPDAofuS01W efib3mMI0u7cKycfRjRwgHLu7kx0DbtU3fTxSEKtBWd/OBzUSDGDtaRsWwByLITcau0h awCC2mc9A0F/7G0LRIndtm4asn+rU+l686oFHl5r3PCHesTYjtfEPPgp5US/NVz7PGqP de9HtboQoGdX9cfOUMIz0ws8IEOcmwIa8Iv+uM/TAQ3gxc51F99lJnPcMiGw4I9QlVQN xyow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777947275; x=1778552075; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=DgBBX+Spc3GcSsocR+N3z63BxmLpev0+iIDdKrva0dY=; b=TvnqktqlJNobmjT9x6rSTim7BltX6A5MCv0MG8ImSd+cuXhWEtmrDw6I6+eHk88zec XwqIQUJOaqP5iV9d9/NVu4QgjkJaz4haanKdVcHTQuuBqO4jw3GKZDl2jmRIFdn4v0vf 6M71ynvlLw5tVDYgsSwaiavv+Dqx9w8N3qGFcLn3bVtpuM9pDBErxA1Fo7Lrf1QVb1Oe ME6OXyujDbngxtBgGi0nGdUYfFLnDJLzeJ0LYbAklCTjMG4Y66yMe2rVpt5jSOAEigLH G7lp0567+amU1tnmzuadcOCkg06hrXkNYmt/lAXW6ZMI9YDCirnKJ2Gm1yLtRjeYXFxR Yi0w== X-Forwarded-Encrypted: i=1; AFNElJ/sVYprNyQ0yPEBEggIIxLRJGz45n/CrMAhBBGfholT/0L+I9+q6qfS/8Apda+A6LjwfH/lN3OauHA=@lists.freedesktop.org X-Gm-Message-State: AOJu0YxyXKCyBC0GcX1qijPjD9Gu3wK0DwjEjPuKvPLUcg4fZlo9EA7I LOoujpJ8dwDqn0cxZS5npisVmIQlEIEsrTuxQsnKyy1Ja/Xn44KCU56wOSkseaPOGxc= X-Gm-Gg: AeBDietRLznw8OJMKFTuM3FCEHX7NdH0H30EVQ2QqTGozoJd8j8AaEhEo7XGiP3kM73 KV9f/mSUjOPPYopmEQuYgKQ+KU/qA6kbL0fYAmQlAlq9HXVGUFRxkQlvqeLLdqBeyK7C809uxmv xLLqxlRfb1+7fXig8pH7VOEMt88a45G+JPAOExEyUHi22pwFLolTjRCxoeHklx/6i6W23yNaUtk E7Rhtkj1yTcQ9QxOl2ty9kVfnTsK0Jrhc1UGay2K7AcuZciIT6Jdw7zDRQXyJgfL3rFOAw+eH4t SLjucVBR9XWxl3pjmMNU2toQPZj6Cbn9bKNxNlDW3QFrq3i7+WnisYOlT5wW6+aQ9FrJhqEbq+k ky0GTVxGWWzjgufUnaAjeaNT2AEeiFzwosMEr7DayUNEvZQFIlST4jJf0aEMhOFQ58E7yPG1gwd 6WzTbLSXzQv00f6FTh3zne6Bcdf6V4BeVqKkzk1EN66gBBfJI= X-Received: by 2002:a05:7022:670c:b0:12d:b43e:435d with SMTP id a92af1059eb24-130a9af04e7mr986271c88.5.1777947274744; Mon, 04 May 2026 19:14:34 -0700 (PDT) Received: from localhost.localdomain ([152.234.115.70]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12df8279e57sm17028963c88.3.2026.05.04.19.14.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2026 19:14:34 -0700 (PDT) From: Ulisses Paixao To: alexander.deucher@amd.com, christian.koenig@amd.com, airlied@gmail.com, simona@ffwll.ch Cc: Ulisses Paixao , Felipe Sousa , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v2] drm/amd/amdgpu: remove duplicated code in gfx_v11 and gfx_v12 Date: Mon, 4 May 2026 23:14:16 -0300 Message-Id: <20260505021417.32520-1-ulissespaixao@usp.br> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Tue, 05 May 2026 07:12:26 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The functions gfx_v11_0_handle_priv_fault and gfx_v12_0_handle_priv_fault share the same logic for searching and triggering a scheduler fault on a ring. This patch moves the shared ring-searching logic to a common function, amdgpu_gfx_handle_priv_fault, in amdgpu_gfx.c. The hardware-specific decoding of ring IDs remains in the version-specific files to maintain proper architectural separation. Signed-off-by: Ulisses Paixao Co-developed-by: Felipe Sousa Signed-off-by: Felipe Sousa --- v2: Keep the HW-specific decoding in gfx_v11_0.c and gfx_v12_0.c. Remove the redundant check for adev->gfx.disable_kq. Simplify the search loop in amdgpu_gfx_handle_priv_fault to iterate over all gfx and compute rings without a switch statement. --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 32 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 27 +-------------------- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 27 +-------------------- 4 files changed, 36 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index b8ca87669..67a291781 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -830,6 +830,38 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id) return r; } +/** + * amdgpu_gfx_handle_priv_fault - Handle privileged instruction fault + * + * @adev: amdgpu_device pointer + * @me_id: micro-engine ID of the faulty ring + * @pipe_id: pipe ID of the faulty ring + * @queue_id: queue ID of the faulty ring + * + * This function handles privileged instruction faults by identifying + * the faulty ring (gfx or compute) and triggering a scheduler fault. + */ +void amdgpu_gfx_handle_priv_fault(struct amdgpu_device *adev, + u8 me_id, u8 pipe_id, u8 queue_id) +{ + struct amdgpu_ring *ring; + int i; + + for (i = 0; i < adev->gfx.num_gfx_rings; i++) { + ring = &adev->gfx.gfx_ring[i]; + if (ring->me == me_id && ring->pipe == pipe_id && + ring->queue == queue_id) + drm_sched_fault(&ring->sched); + } + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + if (ring->me == me_id && ring->pipe == pipe_id && + ring->queue == queue_id) + drm_sched_fault(&ring->sched); + } +} + static void amdgpu_gfx_do_off_ctrl(struct amdgpu_device *adev, bool enable, bool no_delay) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index a0cf0a3b4..0b2f6ce85 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -611,6 +611,8 @@ bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring); bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, int pipe, int queue); +void amdgpu_gfx_handle_priv_fault(struct amdgpu_device *adev, + u8 me_id, u8 pipe_id, u8 queue_id); void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable); int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 2c6f1e25c..888c9f3c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6688,37 +6688,12 @@ static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) { u8 me_id, pipe_id, queue_id; - struct amdgpu_ring *ring; - int i; me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; queue_id = (entry->ring_id & 0x70) >> 4; - if (!adev->gfx.disable_kq) { - switch (me_id) { - case 0: - for (i = 0; i < adev->gfx.num_gfx_rings; i++) { - ring = &adev->gfx.gfx_ring[i]; - if (ring->me == me_id && ring->pipe == pipe_id && - ring->queue == queue_id) - drm_sched_fault(&ring->sched); - } - break; - case 1: - case 2: - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i]; - if (ring->me == me_id && ring->pipe == pipe_id && - ring->queue == queue_id) - drm_sched_fault(&ring->sched); - } - break; - default: - BUG(); - break; - } - } + amdgpu_gfx_handle_priv_fault(adev, me_id, pipe_id, queue_id); } static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 6baac533a..3f0d29372 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5019,37 +5019,12 @@ static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) { u8 me_id, pipe_id, queue_id; - struct amdgpu_ring *ring; - int i; me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; queue_id = (entry->ring_id & 0x70) >> 4; - if (!adev->gfx.disable_kq) { - switch (me_id) { - case 0: - for (i = 0; i < adev->gfx.num_gfx_rings; i++) { - ring = &adev->gfx.gfx_ring[i]; - if (ring->me == me_id && ring->pipe == pipe_id && - ring->queue == queue_id) - drm_sched_fault(&ring->sched); - } - break; - case 1: - case 2: - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i]; - if (ring->me == me_id && ring->pipe == pipe_id && - ring->queue == queue_id) - drm_sched_fault(&ring->sched); - } - break; - default: - BUG(); - break; - } - } + amdgpu_gfx_handle_priv_fault(adev, me_id, pipe_id, queue_id); } static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, -- 2.34.1