From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B254CD4F40 for ; Wed, 13 May 2026 13:18:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AEA1810EE80; Wed, 13 May 2026 13:18:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="CgcgVaZ0"; dkim-atps=neutral Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 297B010EE79 for ; Wed, 13 May 2026 13:18:08 +0000 (UTC) Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id CD3D12F0D; Wed, 13 May 2026 15:17:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1778678278; bh=qlAAHPuyfwHqortEyoSLGkoCaKp5dsbc6D/L7Uu8qiE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CgcgVaZ00ZC/gRlmRFZGJlc9i1nQ9FRvfwoVc/Z7w8FEqeHSo7wLubCqU+arj7ah2 D+VWdUvXndyg8QywPaCSLxvKCrhPL1d5ZSTZatmE+92tXHx2hrPRnh3/CcN7ZhqEPD pT9iaCyqA9v8rzPL9c6X0gbZsUBqDhvC/X5Q4aaY= From: Tomi Valkeinen Date: Wed, 13 May 2026 16:17:32 +0300 Subject: [PATCH v2 10/16] drm/tidss: Add support for DPIENABLE bit MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260513-beagley-ai-display-v2-10-9e9bcefde6bc@ideasonboard.com> References: <20260513-beagley-ai-display-v2-0-9e9bcefde6bc@ideasonboard.com> In-Reply-To: <20260513-beagley-ai-display-v2-0-9e9bcefde6bc@ideasonboard.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Aradhya Bhatia , Nishanth Menon , Vignesh Raghavendra , Swamil Jain , Devarsh Thakkar , Louis Chauvet Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4235; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=qlAAHPuyfwHqortEyoSLGkoCaKp5dsbc6D/L7Uu8qiE=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBqBHn/6E/+DIUFLlIWGpILW9sqFa7vxeqDtI08G VwHofIO+JGJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCagR5/wAKCRD6PaqMvJYe 9TDkD/4x3MiPYu9hRaFX1cGtbr//N7niKSvVzlTqlimNsME+DIQPoa/GBO/2L5DC199fOD+rGjI 81P7oO8yYuwK+OORdt380WW3EI6eIhUX/EGT63Mf90GYMCwtuZZPL2pKb33CFWw1kQgYAWvqqcd fDJuIR/MSJMxlWI4R0xHLP7lh1LmMqInYW+iWfJwrnUy79idDye9FqsS7EdjiiIDcHmkNAHmdAo J8E2mbtTYYyb35goiSa09D0LaeKTqDngI0RePeiFa79aFpmKIaUUKBYEG6KGULqOxYUKyISEhbH y1j6m6bH8jzqeMrjLzqqjSj7KVynVqrUKmnuacKyjeVCO69qYy2afB6ttbRuG7lMrTgD8WEGii1 mhlxlYqZBD3ofIqOgW8HheHmxaW5wWDGFEsa9W5fjXhdfSTUKghsVVc4pC+aTMl40aKafKFvFYk d/qNRt5etaC/QjVeWZRuzMUdaG+oX5LtEKw1d9eXmPYs+rYwImfse3bEE/YvjAUo+CIb+EhWZvh OP5tt/eSwyKywB8BiOLAE/kamBsal1RU8SRF5XEIKElA3w2WMwQlv38wiE03Qq+o1+ByjICFBY8 4LNgFzKRi6q6B5ScALYewk3JIhEtrndZS4zP0XwmfZvBUXatLFshiEo35u46gZ+XXxAPsAoDEUe /Le5O2gk6gJQpFw== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Many (or even all?) K3 SoCs have DSS VP_CONTROL.DPIENABLE bit described in their documentation. This bit controls whether the DPI block is enabled, and is set to 1 by default (i.e. DPI is enabled at HW reset). However, in almost all SoCs the setting does not actually do anything, and at the moment the bit is not managed by the driver. The exception is AM62L, which does have DPIENABLE connected, and disabling the DPI block when it is not in use provides power savings. Let's add a new feature flag for this, 'has_vp_control_dpienable', and implement the support. Disable DPIENABLE for all videoports at resume time, so that it is 0 by default. Specifically enable and disable it in dispc_vp_enable() and dispc_vp_disable() for DPI output. Tested-by: Swamil Jain Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/tidss/tidss_dispc.c | 23 +++++++++++++++++++++-- drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++ drivers/gpu/drm/tidss/tidss_dispc_regs.h | 1 + 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 92cba069ed6c..82e0b3184cc4 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -442,6 +442,8 @@ const struct dispc_features dispc_am62l_feats = { }, .vid_order = {0}, + + .has_vp_control_dpienable = true, }; static const u16 *dispc_common_regmap; @@ -1214,6 +1216,11 @@ void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport) { + if (dispc->feat->has_vp_control_dpienable && + dispc->vp_data[hw_videoport].dpi_output) + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, + DISPC_VP_CONTROL_DPIENABLE_MASK); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, DISPC_VP_CONTROL_ENABLE_MASK); } @@ -1222,6 +1229,11 @@ void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) { VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, DISPC_VP_CONTROL_ENABLE_MASK); + + if (dispc->feat->has_vp_control_dpienable && + dispc->vp_data[hw_videoport].dpi_output) + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, + DISPC_VP_CONTROL_DPIENABLE_MASK); } void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) @@ -2445,10 +2457,17 @@ static void dispc_vp_init(struct dispc_device *dispc) dev_dbg(dispc->dev, "%s()\n", __func__); - /* Enable the gamma Shadow bit-field for all VPs*/ - for (i = 0; i < dispc->feat->num_vps; i++) + for (i = 0; i < dispc->feat->num_vps; i++) { + /* Enable the gamma Shadow bit-field for all VPs*/ VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, DISPC_VP_CONFIG_GAMMAENABLE_MASK); + + if (dispc->feat->has_vp_control_dpienable) { + /* Disable DPIENABLE for all VPs */ + VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONTROL, 0, + DISPC_VP_CONTROL_DPIENABLE_MASK); + } + } } static void dispc_initial_config(struct dispc_device *dispc) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h index 6f53d554259c..0fbfb86adfbf 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -92,6 +92,8 @@ struct dispc_features { u32 num_vids; struct dispc_vid_info vid_info[TIDSS_MAX_PLANES]; u32 vid_order[TIDSS_MAX_PLANES]; + /* The DSS has VP_CONTROL.DPIENABLE bit */ + bool has_vp_control_dpienable; }; extern const struct dispc_features dispc_k2g_feats; diff --git a/drivers/gpu/drm/tidss/tidss_dispc_regs.h b/drivers/gpu/drm/tidss/tidss_dispc_regs.h index 4cdde24d8372..4246c72efdd5 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc_regs.h +++ b/drivers/gpu/drm/tidss/tidss_dispc_regs.h @@ -230,6 +230,7 @@ enum dispc_common_regs { #define DISPC_VP_CONTROL 0x4 #define DISPC_VP_CONTROL_DATALINES_MASK GENMASK(10, 8) +#define DISPC_VP_CONTROL_DPIENABLE_MASK GENMASK(6, 6) #define DISPC_VP_CONTROL_GOBIT_MASK GENMASK(5, 5) #define DISPC_VP_CONTROL_ENABLE_MASK GENMASK(0, 0) -- 2.43.0