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Wed, 13 May 2026 04:57:55 -0500 From: Junhua Shen To: , , , , , , , , , , CC: , , Subject: [PATCH v4 6/6] drm/amdgpu: integrate VRAM migration into SVM range map and fault paths Date: Wed, 13 May 2026 17:57:34 +0800 Message-ID: <20260513095734.69598-7-Junhua.Shen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260513095734.69598-1-Junhua.Shen@amd.com> References: <20260513095734.69598-1-Junhua.Shen@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003444:EE_|DS0PR12MB9446:EE_ X-MS-Office365-Filtering-Correlation-Id: e3cd8346-a441-4950-6083-08deb0d61cfd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700016|376014|82310400026|56012099003|921020|18002099003|22082099003|11063799003; X-Microsoft-Antispam-Message-Info: XXgswftcnj+S5rmEPkD8q+hcYDYAlEOWC1hkUM9sjA8KXAtaONGI11UbAs5KPdWdbdTCwjdY66V/7kJ9wCZsIy6IQU6uX8Vvjn5U58eIwvwnoHZSdffn0A5iR34AarraxsfjWXr+8QM89fhenhgfarzlyxl0t9mnu7C5V4mtUJ/ClMqbdl3RZZUGoZabz8wULKHmAZRNYKdGZbxH6ZzswqIJTXRD/Ogik5Rt+T6JrUsXPaFKT5YrOe3yuICiGNtRjTkAw1WZS8myPFoOInfH6UxgT7iXQpafxBW8Saf/AC6jY6vDj2/guZ/sweyu7xNviZs++vyj9tmtoSaCcAQDtGuMZA4qtZCtLHtvhfU95PRHOewgoYnHtrjMcmoAl1w52ebPdH70XikgAHVmFH/sMIMCDeOyK3O8l2Y0/tJuT8CMMfknCcp8PGtk3Ar1Al7BsPEvKLDKUZ/GZG3w8t+lGkW3/CDaBRX1xTez7UJQ3rdtPDNBOoN/tjwLzjNBeuIc9P0P1tBBLLdIPc0VbSCEq8NnNqGPHM5AE5R24VLl6KvVnjpRUO0AQMmweqn1GBithpNlafk2hMSaJFoSOcSNGkP+wG4cvewLTvYYnWTMcR/E+7cVN09MLmvzoZzaASEQysE6g4c7j6emRtTuwv2SUMHgqsh0YrnsYVxdF4WFmzNG3+DR8OSlrLgeE/baLLfIjaNNYDJqoMEno3oDNFsNmsEKn8jmuwtamB7PZGeRNnjiKn0sR203AfRmlsW7/cYaf+EBSBWajqtZQ8LHRSpEHg== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003444.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9446 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Wire the migration layer into the SVM range map and GPU fault call chains: - Add amdgpu_pagemap_capable() guard in amdgpu_svm_attr_devmem_possible() to disable devmem when pagemap is not supported - Add device_private_page_owner to drm_gpusvm_ctx in both prefetch and fault map contexts - Call amdgpu_svm_range_migrate_range() before GPU mapping in both fault and prefetch paths to perform VRAM migration when preferred - Support AMDGPU_INTERCONNECT_VRAM in amdgpu_svm_range_update_gpu_range() by clearing AMDGPU_PTE_SYSTEM and AMDGPU_PTE_SNOOPED flags for VRAM pages Signed-off-by: Junhua Shen --- drivers/gpu/drm/amd/amdgpu/amdgpu_svm_attr.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_svm_fault.c | 9 ++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_svm_range.c | 21 +++++++++++++++---- 3 files changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_attr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_attr.c index e50b67540c99..115bda12e625 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_attr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_attr.c @@ -25,6 +25,7 @@ #include "amdgpu_svm.h" #include "amdgpu_svm_attr.h" #include "amdgpu.h" +#include "amdgpu_svm_range_migrate.h" #include #include @@ -55,6 +56,9 @@ struct attr_get_ctx { bool amdgpu_svm_attr_devmem_possible(struct amdgpu_svm *svm, const struct amdgpu_svm_attrs *attrs) { + if (!amdgpu_pagemap_capable(svm)) + return false; + if (svm->adev->apu_prefer_gtt) return false; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_fault.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_fault.c index 7763eb029eaa..b5d21a66a228 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_fault.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_fault.c @@ -26,6 +26,8 @@ #include "amdgpu_svm_attr.h" #include "amdgpu_svm_fault.h" #include "amdgpu_svm_range.h" +#include "amdgpu_svm_range_migrate.h" +#include "amdgpu_migrate.h" #include "amdgpu.h" #include "amdgpu_vm.h" #include "amdgpu_gmc.h" @@ -153,13 +155,14 @@ static int amdgpu_svm_range_map_fault(struct amdgpu_svm *svm, const struct amdgpu_svm_attrs *attrs = &attr_range->attrs; bool devmem_possible = amdgpu_svm_attr_devmem_possible(svm, attrs); bool need_vram_migration = amdgpu_svm_attr_prefer_vram(svm, attrs); - devmem_possible = false; /* TODO: add migration */ struct drm_gpusvm_ctx map_ctx = { .read_only = !!(attrs->flags & AMDGPU_SVM_ATTR_BIT_GPU_RO), .devmem_possible = devmem_possible, .check_pages_threshold = devmem_possible ? SZ_64K : 0, .devmem_only = need_vram_migration && devmem_possible, .timeslice_ms = need_vram_migration && devmem_possible ? 5 : 0, + .device_private_page_owner = devmem_possible ? + AMDGPU_PGMAP_OWNER(svm->adev) : NULL, }; struct amdgpu_svm_range *range; ktime_t timestamp = ktime_get_boottime(); @@ -228,7 +231,9 @@ static int amdgpu_svm_range_map_fault(struct amdgpu_svm *svm, } AMDGPU_SVM_RANGE_DEBUG(range, "PAGE FAULT"); - /* TODO: add migration*/ + if (need_vram_migration) + amdgpu_svm_range_migrate_range(svm, &range->base, + AMDGPU_SVM_MIGRATE_TO_VRAM); AMDGPU_SVM_RANGE_DEBUG(range, "GET PAGES"); ret = amdgpu_svm_range_get_pages(svm, &range->base, &map_ctx); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_range.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_range.c index fe543a16b399..b77f3a52f3ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_range.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_svm_range.c @@ -26,6 +26,8 @@ #include "amdgpu_svm_attr.h" #include "amdgpu_svm_range.h" #include "amdgpu_svm_fault.h" +#include "amdgpu_svm_range_migrate.h" +#include "amdgpu_migrate.h" #include "amdgpu.h" #include "amdgpu_vm.h" @@ -244,9 +246,11 @@ amdgpu_svm_range_update_gpu_range(struct amdgpu_svm *svm, unsigned long seg_pages = min_t(unsigned long, 1UL << entry->order, npages - mapped_pages); unsigned long start_page, last_page; + uint64_t seg_pte_flags = pte_flags; bool is_last_seg; - if (entry->proto != DRM_INTERCONNECT_SYSTEM) + if (entry->proto != DRM_INTERCONNECT_SYSTEM && + entry->proto != AMDGPU_INTERCONNECT_VRAM) return -EOPNOTSUPP; start_page = range_start_page + mapped_pages; @@ -254,9 +258,13 @@ amdgpu_svm_range_update_gpu_range(struct amdgpu_svm *svm, mapped_pages += seg_pages; is_last_seg = mapped_pages == npages; + /* For VRAM pages, clear the SYSTEM and SNOOPED bits */ + if (entry->proto == AMDGPU_INTERCONNECT_VRAM) + seg_pte_flags &= ~(AMDGPU_PTE_SYSTEM | AMDGPU_PTE_SNOOPED); + ret = amdgpu_vm_update_range(svm->adev, svm->vm, false, false, flush_tlb && is_last_seg, true, NULL, - start_page, last_page, pte_flags, + start_page, last_page, seg_pte_flags, 0, entry->addr, NULL, NULL, wait_fence && is_last_seg ? fence : NULL); if (ret) @@ -365,12 +373,13 @@ amdgpu_svm_range_map_attrs(struct amdgpu_svm *svm, int ret; bool devmem_possible = amdgpu_svm_attr_devmem_possible(svm, attrs); bool need_vram_migration = amdgpu_svm_attr_prefer_vram(svm, attrs); - devmem_possible = false; /* TODO: add migration */ struct drm_gpusvm_ctx map_ctx = { .read_only = !!(attrs->flags & AMDGPU_SVM_ATTR_BIT_GPU_RO), .devmem_possible = devmem_possible, .devmem_only = need_vram_migration && devmem_possible, .check_pages_threshold = devmem_possible ? SZ_64K : 0, + .device_private_page_owner = devmem_possible ? + AMDGPU_PGMAP_OWNER(svm->adev) : NULL, }; while (addr < end) { @@ -399,7 +408,11 @@ amdgpu_svm_range_map_attrs(struct amdgpu_svm *svm, continue; } - /* TODO: add migration */ + if (need_vram_migration) { + AMDGPU_SVM_RANGE_DEBUG(range, "PREFETCH - MIGRATION PAGES"); + amdgpu_svm_range_migrate_range(svm, &range->base, + AMDGPU_SVM_MIGRATE_TO_VRAM); + } AMDGPU_SVM_RANGE_DEBUG(range, "PREFETCH - GET PAGES"); -- 2.34.1