From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6151CD4F3C for ; Fri, 15 May 2026 05:09:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A9FB10F3DB; Fri, 15 May 2026 05:09:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; secure) header.d=pm.me header.i=@pm.me header.b="Ijru+n1y"; dkim-atps=neutral Received: from mail-106118.protonmail.ch (mail-106118.protonmail.ch [79.135.106.118]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9A81710F3DB; Fri, 15 May 2026 05:09:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1778821755; x=1779080955; bh=wpiHLX1zWOUy8hBTDFwvSmMkzZNlxTZRLe+LwVa3mZQ=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=Ijru+n1yq4d5K79UiEOOTgNDmbbqldJazRLtiTFMNiV0aEzJHk52zV4v4flBwofmu 9nkUYrEgFphCTZB+igkolrAcEDn0o+N0f7V2dqjq5nJzKlWd3h+W49RTjRta19SYD3 x4UZ+t2oBiD9kY22uIHSBpVkgMPEoeG2dQKVk16wTIT+gDz50ObDeYspr4MZvGF7QY kp6/40NdAkHZA3CAdnLBzG0u3X/Hkp+9uaL9rjHO0QR8E9P5GHUQOhJqPKW2qyvGfm Oc/gdqtrF8kT4GAY1Hhkb9y0M96U4tnTmJ7hsZSC0CkxBOjWdo4lBxi2b9Xcm4dFC5 Y8x9Fsf897FcQ== Date: Fri, 15 May 2026 05:09:08 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Konrad Dybcio Subject: [PATCH RFC v6 5/7] drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature Message-ID: <20260515-adreno-810-v6-5-fbe04c7203e1@pm.me> In-Reply-To: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> References: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: deabef54c61baff43a06462424b7511c88efdcf4 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" A8XX GPUs have two sets of protect registers: 64 global slots and 16 pipe specific slots. The last-span-unbound feature is only available on pipe protect registers, and should always target pipe slot 15. This matches the downstream driver which hardcodes pipe slot 15 for all A8XX GPUs (GRAPHICS.LA.15.0.r1) and resolves protect errors on A810. Reviewed-by: Konrad Dybcio Reviewed-by: Akhil P Oommen Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index d519a29573a1..74802f330ae9 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -265,8 +265,8 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) =09 * Last span feature is only supported on PIPE specific register. =09 * So update those here =09 */ -=09a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_m= ax), final_cfg); -=09a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_m= ax), final_cfg); +=09a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); +=09a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); =20 =09a8xx_aperture_clear(gpu); } --=20 2.53.0