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This feature is required to limit the peak current consumption to avoid HW spec violation on GX/MX rails. Add the necessary HFI interface support to pass the recommended CLX and IFF/PCLX limits tables to the GMU. Per-GPU configuration is consumed from the catalog entries. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 15 ++++++++ drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 71 +++++++++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index eb431e5e00b1..f6a3f1924bb3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -34,6 +34,19 @@ struct cpu_gpu_lock { uint64_t regs[62]; }; +struct a6xx_limits_tbl { + /** @tbl: List of limits table **/ + struct a6xx_hfi_limits_tbl *tbl; + /** @count: Number of entries in the list **/ + u32 count; +}; + +#define DECLARE_ADRENO_LIMITS_TABLE(name) \ +static const struct a6xx_limits_tbl name = { \ + .tbl = name ## _tbl, \ + .count = ARRAY_SIZE(name ## _tbl), \ +} + /** * struct a6xx_info - a6xx specific information from device table * @@ -54,6 +67,8 @@ struct a6xx_info { u32 gmu_cgc_mode; u32 prim_fifo_threshold; const struct a6xx_bcm *bcms; + const struct a6xx_hfi_clx_table_v2_cmd *clx_tbl; + const struct a6xx_limits_tbl *limits_tbl; }; struct a6xx_gpu { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index 487c2736f2b3..13ae34d0d898 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -886,6 +886,73 @@ static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu) return 0; } +static int a6xx_hfi_enable_iff_pclx(struct a6xx_gmu *gmu, const struct a6xx_limits_tbl *limits) +{ + struct a6xx_hfi_table_entry *entry; + struct a6xx_hfi_table *tbl; + size_t entry_size; + size_t size; + int ret; + + if (!limits) + return 0; + + ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_IFF_PCLX, 1, 0); + if (ret) { + DRM_DEV_ERROR(gmu->dev, "Unable to enable IFF PCLX (%d)\n", ret); + return ret; + } + + entry_size = limits->count * sizeof(struct a6xx_hfi_limits_tbl); + size = sizeof(*tbl) + sizeof(*entry) + entry_size; + + tbl = kzalloc(size, GFP_KERNEL); + if (!tbl) + return -ENOMEM; + + tbl->type = HFI_TABLE_LIMITS_MIT; + entry = &tbl->entry[0]; + entry->count = limits->count; + entry->stride = sizeof(struct a6xx_hfi_limits_tbl) >> 2; + + memcpy(entry->data, limits->tbl, entry_size); + + ret = a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_TABLE, tbl, size, NULL, 0); + if (ret) + DRM_DEV_ERROR(gmu->dev, "Unable to send PCLX table (%d)\n", ret); + + kfree(tbl); + return ret; +} + +static int a6xx_hfi_enable_clx(struct a6xx_gmu *gmu) +{ + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + const struct a6xx_info *info = adreno_gpu->info->a6xx; + struct a6xx_hfi_clx_table_v2_cmd cmd = { 0 }; + int ret; + + if (!info->clx_tbl) + return 0; + + ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_CLX, 1, 0); + if (ret) { + DRM_DEV_ERROR(gmu->dev, "Unable to enable CLX (%d)\n", ret); + return ret; + } + + memcpy(&cmd, info->clx_tbl, sizeof(cmd)); + + ret = a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_CLX_TBL, &cmd, sizeof(cmd), NULL, 0); + if (ret) { + DRM_DEV_ERROR(gmu->dev, "Unable to send CLX table (%d)\n", ret); + return ret; + } + + return a6xx_hfi_enable_iff_pclx(gmu, info->limits_tbl); +} + static int a6xx_hfi_send_test(struct a6xx_gmu *gmu) { struct a6xx_hfi_msg_test msg = { 0 }; @@ -987,6 +1054,10 @@ int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state) if (ret) return ret; + ret = a6xx_hfi_enable_clx(gmu); + if (ret) + return ret; + ret = a6xx_hfi_enable_ifpc(gmu); if (ret) return ret; -- 2.51.0