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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a90f10c78csm5128907e87.14.2026.05.20.07.52.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 07:52:00 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 20 May 2026 17:51:31 +0300 Subject: [PATCH v5 24/28] soc: qcom: ubwc: drop ubwc_bank_spread MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260520-ubwc-rework-v5-24-72f2749bc807@oss.qualcomm.com> References: <20260520-ubwc-rework-v5-0-72f2749bc807@oss.qualcomm.com> In-Reply-To: <20260520-ubwc-rework-v5-0-72f2749bc807@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5607; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=ELfSfo30Xq2szDKMHs49lszh5EmDwoOzMcxayrSn7iI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBqDcpp4I7RvK2HILsybRcgfmEkL+/9WfJirTkYA jDZw6s3r+WJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCag3KaQAKCRCLPIo+Aiko 1ZJtB/4lsnTD7zdhZblkKl3eH/4SO3fLhhOuwa4VE2DtFikTLo1feLEogub0Xnbt7lFGtEF2rnU ykylJ7mH7bAfx+pxxBKKLKZNUUtlOcALJUQNoxjBl0vVv9eBn7z5opObMqTIxHwpV1o+7FS24+E FXiZJbcNJecaCNnQ0Gx0za3x4RqGSrJHHTkPCyJ4ScJdGthN+hU4nNiqZjuDF1NuIM8Ugyvlx4J UcCdw6sBFejsMj9X6fsPTrCfaBc4aXE7tgPEDngnGeTPX3AVuak3VcXQlro2twryZVLFxwPNXZY ed1JltJJfETWGoRF97wvd0bg15A0pKvuBdE/Y/BJNao25Mbo X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: g33wznWHsMyfkxFDL3BmmFkqupFHFxVD X-Authority-Analysis: v=2.4 cv=e5k2j6p/ c=1 sm=1 tr=0 ts=6a0dca93 cx=c_pps a=ULNsgckmlI/WJG3HAyAuOQ==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=VGmcmSc_WkMUHOMtpCQA:9 a=QEXdDO2ut3YA:10 a=1WsBpfsz9X-RYQiigVTh:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE0NSBTYWx0ZWRfX02wTO4EN2l62 n6jqD1u8EM4LheFnGc7PjFqbhMH8RrOiATEKA47T3fcxoLnoDxAzn7bh9DoREb9bJVzCbDhpaQQ 4kAVeUSRAHAuiKyks3qT19wM3FS6KouGSna/7YSGQLp0p0P3OLQ+WMrOLldoa/RPFL8JikEPXA6 bQHq8Ehj0fJF1olJE2+9zf1/Q+YcX/hE7co3iWyEcmTsMLrE3dRlOOr9gdSD3M4v4Scf1pHFdGr GmFi+o9x1fHFVPrqMAaK8yC6C+uT7szailGiKGcPsP1K5aygn1jibu5aXItJlJOLppFw2iQVpZz Ay35xBel8kW1pyPOrhtVmp5pKHDJIVpTszsop3Uefb7zccxu4l0V8mat2LJnhM04HZMwAC57BS1 MM1QzwLQNtnbGCLgR+Ds+Bo78Bn1ywzWZ5nB1f5yaPAo1EopoMhsnrQXf1edlDjHFPJPqUPn02j wJvCEIcCyuiobqWnkGw== X-Proofpoint-GUID: g33wznWHsMyfkxFDL3BmmFkqupFHFxVD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200145 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" According to the documentation, UBWC bank spreading should be enabled for all targets. It's just not all targets have separate bit to control it. Drop the bit from the database and make the helper always return true. If we need to change it later, the helper can be adjusted according to the programming guides. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/ubwc_config.c | 14 -------------- include/linux/soc/qcom/ubwc.h | 3 +-- 2 files changed, 1 insertion(+), 16 deletions(-) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 1344cda0fb75..35cde4e9a238 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -20,7 +20,6 @@ static const struct qcom_ubwc_cfg_data eliza_data = { .ubwc_enc_version = UBWC_5_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 14 for LP_DDR4 */ .highest_bank_bit = 15, .macrotile_mode = true, @@ -30,7 +29,6 @@ static const struct qcom_ubwc_cfg_data kaanapali_data = { .ubwc_enc_version = UBWC_6_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 16, .macrotile_mode = true, }; @@ -59,7 +57,6 @@ static const struct qcom_ubwc_cfg_data qcm2290_data = { static const struct qcom_ubwc_cfg_data sa8775p_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 13, .macrotile_mode = true, }; @@ -68,7 +65,6 @@ static const struct qcom_ubwc_cfg_data sar2130p_data = { .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 13, .macrotile_mode = true, }; @@ -77,7 +73,6 @@ static const struct qcom_ubwc_cfg_data sc7180_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 14, }; @@ -85,7 +80,6 @@ static const struct qcom_ubwc_cfg_data sc7280_data = { .ubwc_enc_version = UBWC_3_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 14, .macrotile_mode = true, }; @@ -102,7 +96,6 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 16, .macrotile_mode = true, }; @@ -126,7 +119,6 @@ static const struct qcom_ubwc_cfg_data sm6115_data = { .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 14, }; @@ -149,7 +141,6 @@ static const struct qcom_ubwc_cfg_data sm6350_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, .highest_bank_bit = 14, }; @@ -171,7 +162,6 @@ static const struct qcom_ubwc_cfg_data sm8250_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, .macrotile_mode = true, @@ -181,7 +171,6 @@ static const struct qcom_ubwc_cfg_data sm8350_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, .macrotile_mode = true, @@ -191,7 +180,6 @@ static const struct qcom_ubwc_cfg_data sm8550_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, - .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, .macrotile_mode = true, @@ -200,7 +188,6 @@ static const struct qcom_ubwc_cfg_data sm8550_data = { static const struct qcom_ubwc_cfg_data sm8750_data = { .ubwc_enc_version = UBWC_5_0, .ubwc_swizzle = 6, - .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, .macrotile_mode = true, @@ -209,7 +196,6 @@ static const struct qcom_ubwc_cfg_data sm8750_data = { static const struct qcom_ubwc_cfg_data glymur_data = { .ubwc_enc_version = UBWC_5_0, .ubwc_swizzle = 0, - .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, .macrotile_mode = true, diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index c3f9efae5db8..254721f5ea3c 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -33,7 +33,6 @@ struct qcom_ubwc_cfg_data { * DDR bank. This should ideally use DRAM type detection. */ int highest_bank_bit; - bool ubwc_bank_spread; /** * @macrotile_mode: Macrotile Mode @@ -85,7 +84,7 @@ static inline bool qcom_ubwc_macrotile_mode(const struct qcom_ubwc_cfg_data *cfg static inline bool qcom_ubwc_bank_spread(const struct qcom_ubwc_cfg_data *cfg) { - return cfg->ubwc_bank_spread; + return true; } static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg) -- 2.47.3