From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4AC9FCD4F3D for ; Wed, 20 May 2026 16:25:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A049D10F0D4; Wed, 20 May 2026 16:25:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.b="OSzJ6JNe"; dkim=pass (2048-bit key; unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="gh6w0P+Q"; dkim-atps=neutral Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3631510F0DE for ; Wed, 20 May 2026 16:25:31 +0000 (UTC) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64KE6Z7Q119076 for ; Wed, 20 May 2026 16:25:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=4tfvGKSXQFo neM9FUCAjiWpETYTjQZebXY53uh3TIBc=; b=OSzJ6JNeTRAEmkyk4ib8Je9znbU QxqMpnkvTSbV3obsudtRWqGYeXHoxzDErlUwe5+ntovtHlvNogCURJc1HSAQordo BFvoHu7EtxDwYxXlaV0nTlrQNfc+svmvlpKydAp2B+nMsgcUpxDN1R3XT4Ip+le+ MqLuUgmCmFs5psz7RHBPqfrtHvIvLN/tYhazGzYs9ati+jDOUUs4kSaU4wneiXUr RfG8Q4ZdQEb62iNI96XkqjEJMpPX9mS/kcJNxasHMys2gwj7IzxPKqbns1HPiWsr snkYzIjatTfDxlK71xo5NDplUZbLDbqvGt/+hVgj8x2CFtPY7e/ekpq01nA== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e9ee88n60-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 20 May 2026 16:25:30 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-82f85179263so7289285b3a.3 for ; Wed, 20 May 2026 09:25:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779294330; x=1779899130; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4tfvGKSXQFoneM9FUCAjiWpETYTjQZebXY53uh3TIBc=; b=gh6w0P+QqHS0Nqm9ALvr+MeuV4eRkoZ4MUaGlgZQQGk6SC9t1ewD4Tt2xs/UKwNech Yp5wcXvQ5FlX8Tdis/X2Hs+MxOEpiftNqNFOPs7m+RFVQ9nwZtauoihiwt+YLARcY3fj Y9jTViR81NkQX3VkQDcgIaPk5ybMcN9KMeIlX/u4n1RqNDATTBx2JvYyjdX+62Pdd30P p2OjPc4QE+on5NA7EkPTSrlVmiA8cZTkJZ3ti0L4Ml/mggChuuREp1Ex8X9OHlWI5+TL n7vDkS5GsH9IEwZM9XUJnLb9cTB4SKFDNmubwiPaj+REs2MewtCrmobC/5O6RNCuAyf/ IFLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779294330; x=1779899130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=4tfvGKSXQFoneM9FUCAjiWpETYTjQZebXY53uh3TIBc=; b=ovMA1JtyOWIk7AKIJT3u40q9+ETIdqV35yWJU9DnsOhK6WUL+ZmIPoAGg1lvoEL/ss Fb7Mbs+nuc8gbGkEhyq7RS9pldY7l1nUzdhRV3635X61GT+KQzKB3B7M+U0jkuGnlolS rgvlyWQr53BY0vpJUkoXMoQUaM6tX+1xbx77PnLp77y2UhdEwhpqyjtU+ys6ziPU8F74 QYDJWpVOYIxI/ph50WhT7s5h+gGNUaeT6B21N0aiW+aksq1HcvNijshHmVEX0Ng9i0QK Tet9Oacp5b9QRdZnJMJOmyScue4ximAqEs2/LaJVRRvJOQZgOO8TWNHH2jH2eBupMy8j zOUw== X-Gm-Message-State: AOJu0YxUQ40hRwnqpHf5mnDzQ8Hz0S/kyxlvjRpHaptr8eQRcjh4N6mW SCwAYUMU5+ZrZ0iAiTZwPaDLFWt2OY8HxM/njdiyHB7sTcmi+hrvdpyjuxTCyUhUt0d336W4YZd pHRzpOZnAoaqVISQIrvhNIy2IstxAdQb0vt+XDzlLzwl/45YdWku6Xwve0mMBJju0cWlPILemYi bnWlg= X-Gm-Gg: Acq92OGHXXufsrzCSpRVnBuKaSs0DWJxuJKReePYO2vUl+C9WdLGhRmG4BUAC6bbyED q/DFfjGwMRQiq0uGCCYpqc+9dMxRsiqsywGURIjIo5iqcTGJ6VLnzUASKzPvwgEe0mDzd/pjZXR U4OpDnaAA/L2UTwZ2WWM1AuN1IVuODpmIbsKlMWWBSg3LJ8IhXbz4IRe+Byv8oc7pbvUvO/dfqB M04WcyPuulERwOC4u+RyOk0EzzzF08IFPUgDJDPsoEw5IPhQ2f5lEC8Fm2Hy3AGIjDs4K2Djtrs +SUHoYExLKS0GgsVYGYfjAkl7TnL2SCSdX5QKseDvY6l6UmB27ztXtXPwyWCZAN4uFUgPwgAgN+ s4QUkzm+KJHVVK7x6XwNRuWxO46GetlMk X-Received: by 2002:a05:6a00:a207:b0:837:80a:5aaa with SMTP id d2e1a72fcca58-83f33ce682cmr27275519b3a.45.1779294329958; Wed, 20 May 2026 09:25:29 -0700 (PDT) X-Received: by 2002:a05:6a00:a207:b0:837:80a:5aaa with SMTP id d2e1a72fcca58-83f33ce682cmr27275472b3a.45.1779294329396; Wed, 20 May 2026 09:25:29 -0700 (PDT) Received: from localhost ([2601:1c0:5000:d5c:4ec8:83f5:8254:6891]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f19c5c020sm21739290b3a.30.2026.05.20.09.25.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 09:25:29 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Anna Maniscalco , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v8 07/16] drm/msm: Add sysprof accessors Date: Wed, 20 May 2026 09:23:54 -0700 Message-ID: <20260520162454.18391-8-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260520162454.18391-1-robin.clark@oss.qualcomm.com> References: <20260520162454.18391-1-robin.clark@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: did7vpr-nRRZD1QbKKlUbhe5Srx0dKWK X-Authority-Analysis: v=2.4 cv=e5k2j6p/ c=1 sm=1 tr=0 ts=6a0de07a cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=v4b4B-quZFKF0PxyZCUA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1OSBTYWx0ZWRfX6ngmli6mI7RB 6cflQ238BUmuhWokaSJLxFHGGKbVydXFOwAVBEV5UNr2iSQJbndEAaP03z8kRqnBxlMdgH3otSk Zb4P4qK7I2s79ksLugGNqEhdxahIuMj2k+ZM+xbkYaazIkqObRTHZClFzVqnyPlJ4HKS4TKmOZ/ /aCPAmU91INx0Puvqlx0d+4tS80isAo3Rxl6Q4rdl1RNpa0guhhcEXnexlRCIZJv5FD0f+bJUje De/XMJEbRBQZpEJ/GqQ2ifezUbNJFnDVAOOL9Q1OxLy9gJLBe9N9gxZaCVeABgJqJYpErGxY7cs MJ83XWvYiis/2o5Y/cLhEel+CkGvPquhDZo7xYwO9qcRPXRhfyHO7TneDQcVQMFe+7xNBCdBAq6 K70BCYrheKZbvTsWZLuvXs6pnbmT6uH+42LGtzg73326O2KH9MMmwNDrj7j+Siq832aF8y9Yuy8 Y2fZltRfRvb52nGrk2w== X-Proofpoint-GUID: did7vpr-nRRZD1QbKKlUbhe5Srx0dKWK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200159 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently the sysprof param serves two functions, (a) disabling perfcntr clearing on context switch/preemption, and (b) disabling IFPC. In the future, with kernel side global perfcntr collection/stream, the decision about disabling IFPC will change. To prepare for this, split out two helpers/accessors for the two different cases. For now, they are the same thing, but this will change. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 +++----- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 +++-- drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 2 +- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a8xx_preempt.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 18 ++++++++++++++++++ 6 files changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 1b44b9e21ad8..aba08fb76249 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2036,10 +2036,10 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) { + bool sysprof = msm_gpu_sysprof_no_ifpc(gpu); struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; - unsigned int sysprof_active; /* Nothing to do if GPU is suspended. We will handle this during GMU resume */ if (!pm_runtime_get_if_active(&gpu->pdev->dev)) @@ -2047,15 +2047,13 @@ void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) mutex_lock(&gmu->lock); - sysprof_active = refcount_read(&gpu->sysprof_active); - /* * 'Perfcounter select' register values are lost during IFPC collapse. To avoid that, * use the currently unused perfcounter oob vote to block IFPC when sysprof is active */ - if ((sysprof_active > 1) && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) + if (sysprof && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); - else if ((sysprof_active == 1) && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) + else if (!sysprof && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET); mutex_unlock(&gmu->lock); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 727281fbef36..71f54ab5425d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -203,7 +203,7 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, struct msm_ringbuffer *ring, struct msm_gem_submit *submit) { - bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; + bool sysprof = msm_gpu_sysprof_no_perfcntr_zap(&a6xx_gpu->base.base); struct msm_context *ctx = submit->queue->ctx; struct drm_gpuvm *vm = msm_context_vm(submit->dev, ctx); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; @@ -1608,7 +1608,7 @@ static int hw_init(struct msm_gpu *gpu) a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); } - if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) { + if (!ret && msm_gpu_sysprof_no_ifpc(gpu)) { ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); if (!ret) set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); @@ -2854,6 +2854,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a8xx_progress, + .sysprof_setup = a6xx_gmu_sysprof_setup, }, .init = a6xx_gpu_init, .get_timestamp = a8xx_gmu_get_timestamp, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c index df4cbf42e9a4..1e599d4ddea1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c @@ -261,7 +261,7 @@ void a6xx_preempt_trigger(struct msm_gpu *gpu) mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000)); /* Enable or disable postamble as needed */ - sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; + sysprof = msm_gpu_sysprof_no_perfcntr_zap(gpu); if (!sysprof && !a6xx_gpu->postamble_enabled) preempt_prepare_postamble(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index ccfccc45133f..e022c9a162a4 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -849,7 +849,7 @@ static int hw_init(struct msm_gpu *gpu) */ a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); - if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) { + if (!ret && msm_gpu_sysprof_no_perfcntr_zap(gpu)) { ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); if (!ret) set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_preempt.c b/drivers/gpu/drm/msm/adreno/a8xx_preempt.c index 3d8c33ba722e..6cb53a071801 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_preempt.c @@ -242,7 +242,7 @@ void a8xx_preempt_trigger(struct msm_gpu *gpu) mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000)); /* Enable or disable postamble as needed */ - sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; + sysprof = msm_gpu_sysprof_no_perfcntr_zap(gpu); if (!sysprof && !a6xx_gpu->postamble_enabled) preempt_prepare_postamble(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 8c08dc065372..9e5c753437c2 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -311,6 +311,24 @@ static inline bool msm_gpu_active(struct msm_gpu *gpu) return false; } +static inline bool +msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu) +{ + return refcount_read(&gpu->sysprof_active) > 1; +} + +static inline bool +msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu) +{ + /* + * For now, this is the same condition as disabling perfcntr clears + * on context switch. But once kernel perfcntr IFPC support is in + * place, we will only need to disable IFPC for legacy userspace + * setting SYSPROF param. + */ + return msm_gpu_sysprof_no_perfcntr_zap(gpu); +} + /* * The number of priority levels provided by drm gpu scheduler. The * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some -- 2.54.0