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Fri, 22 May 2026 10:35:03 -0700 (PDT) X-Received: by 2002:a17:903:2f03:b0:2bd:eeb6:ff28 with SMTP id d9443c01a7336-2beb0672a53mr56264985ad.12.1779471303286; Fri, 22 May 2026 10:35:03 -0700 (PDT) Received: from localhost ([2601:1c0:5000:d5c:4ec8:83f5:8254:6891]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb56d750asm23344045ad.33.2026.05.22.10.35.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2026 10:35:02 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Rob Clark , Anna Maniscalco , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v9 15/16] drm/msm/a6xx: Append SEL regs to dyn pwrup reglist Date: Fri, 22 May 2026 10:33:01 -0700 Message-ID: <20260522173349.55491-16-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260522173349.55491-1-robin.clark@oss.qualcomm.com> References: <20260522173349.55491-1-robin.clark@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: FL7K9vF8vQSsbM2zVm5pRPeohodtAlwt X-Authority-Analysis: v=2.4 cv=JrbBas4C c=1 sm=1 tr=0 ts=6a1093c8 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=gjKahejJLxXXi_JFjLAA:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: FL7K9vF8vQSsbM2zVm5pRPeohodtAlwt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIyMDE3NSBTYWx0ZWRfX4fr4aAOHSVpD WyVHQwTmCfEO7Y4UirLewd3psEiGYmezkQILI81KI4lfy34BMcf/6Jsg5BX4k3Hz8Sn2YOXforv hhY7LxvdaP411++8mMSjZgbLa10JTtSk6F+pQE2olDa+J0xtlLfw713br7bsqgmAqEvcMB3osR9 9sR48CdCTI5LIGUViCDIB+r0Ouoc/Z5/t3UYFRLIIKwonVn1sS05/Wln7YuqSpbevH9Zpn94ucA fR0kQjiIpx7GLodNV4a4OpCkn4sonWenzRtcCV/MvtRrl/PZygEEXrNpcu5n+8YpPRm5I704TKb K02deFKw+JEdWSAWROeKHbDF1jL+abP7KFa4SL/F9aHHqWaBvynIOOIbpayTk5aefY9j4hPX6pS x5XP7rVIyNmJaz0pbeYr9s1VLyBfw+n3MbKaVYjZXT7aKwHos/jiGlBVUFo5BJ9djcPxRUqmUIi /h7RehGOmYw/sc91vGg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-22_04,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605220175 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This is needed so that SEL reg values are restored on exit from IFPC. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 84 +++++++++++++++++++++++++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 11 +++- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 1 + 3 files changed, 89 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index e6c362c55dee..af524130d5c4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -946,6 +946,7 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE)); } lock->dynamic_list_len = dyn_pwrup_reglist_count; + a6xx_gpu->dynamic_sel_reglist_offset = dyn_pwrup_reglist_count; } static int a7xx_preempt_start(struct msm_gpu *gpu) @@ -2535,11 +2536,60 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } +static void +perfcntr_select(struct msm_ringbuffer *ring, enum adreno_pipe pipe, + uint32_t regidx, uint32_t *countables, uint32_t nr, + uint32_t **reglist) +{ + OUT_PKT4(ring, regidx, nr); + for (unsigned i = 0; i < nr; i++) + OUT_RING(ring, countables[i]); + + if (!*reglist) + return; + + for (unsigned i = 0; i < nr; i++) { + /* + * Bitfield is in same position on a7xx, but only 2 bits.. + * which is sufficient for NONE/BR/BV: + */ + *(*reglist)++ = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe); + *(*reglist)++ = regidx + i; + *(*reglist)++ = countables[i]; + } +} + static void a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, const struct msm_perfcntr_stream *stream) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); enum adreno_pipe pipe = PIPE_NONE; + uint32_t *reglist = NULL; + uint32_t *reglist_sel_start; + + if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) { + WARN_ON(!a6xx_gpu->pwrup_reglist_emitted); + + struct cpu_gpu_lock *lock = a6xx_gpu->pwrup_reglist_ptr; + int off = (2 * lock->ifpc_list_len) + + (2 * lock->preemption_list_len) + + (3 * a6xx_gpu->dynamic_sel_reglist_offset); + + reglist = (uint32_t *)&lock->regs[0]; + reglist += off; + reglist_sel_start = reglist; + + /* Clear any previously configured SEL reg entries: */ + lock->dynamic_list_len = a6xx_gpu->dynamic_sel_reglist_offset; + + /* + * Ensure CP sees the dynamic_list_len update before we + * start modifying the SEL entries: + */ + dma_wmb(); + } for (unsigned i = 0; i < stream->nr_groups; i++) { unsigned group_idx = msm_perfcntr_group_idx(stream, i); @@ -2567,17 +2617,15 @@ a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, const struct msm_perfcntr_counter *counter = &group->counters[base]; unsigned nr = group_state->allocated_counters; - OUT_PKT4(ring, counter->select_reg, nr); - for (unsigned c = 0; c < nr; c++) - OUT_RING(ring, group_state->countables[c]); + perfcntr_select(ring, pipe, counter->select_reg, + group_state->countables, nr, ®list); for (unsigned s = 0; s < ARRAY_SIZE(counter->slice_select_regs); s++) { if (!counter->slice_select_regs[s]) break; - OUT_PKT4(ring, counter->slice_select_regs[s], nr); - for (unsigned c = 0; c < nr; c++) - OUT_RING(ring, group_state->countables[c]); + perfcntr_select(ring, pipe, counter->slice_select_regs[s], + group_state->countables, nr, ®list); } } @@ -2591,6 +2639,30 @@ a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, OUT_RING(ring, upper_32_bits(rbmemptr(ring, perfcntr_fence))); OUT_RING(ring, stream->sel_fence); + /* + * Update the pwrup reglist size before flushing. Kgsl does a shared- + * memory spinlock dance with SQE to avoid racing with IFPC exit. But + * we can skip that since the ringbuffer programming will be executed + * by SQE after dynamic reglist size is updated. So even if we lose + * the race, the register programming in the rb will overwrite/correct + * the SEL regs restored by SQE on IFPC exit, before sampling begins. + */ + if (reglist) { + struct cpu_gpu_lock *lock = a6xx_gpu->pwrup_reglist_ptr; + unsigned nr_regs = (reglist - reglist_sel_start) / 3; + + /* + * Ensure CP sees updates to the pwrup_reglist before it + * sees the new (increased) length: + */ + dma_wmb(); + + /* Update dynamic reglist len to include new SEL reg programming: */ + lock->dynamic_list_len = a6xx_gpu->dynamic_sel_reglist_offset + nr_regs; + + WARN_ON_ONCE(reglist > (uint32_t *)((uint8_t *)lock + PWRUP_REGLIST_SIZE)); + } + a6xx_flush_yield(gpu, ring); /* Check to see if we need to start preemption */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index d3f0b40787db..b72fb58bf223 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -21,17 +21,19 @@ struct cpu_gpu_lock { uint32_t cpu_req; uint32_t turn; union { + /* a6xx: */ struct { uint16_t list_length; uint16_t list_offset; }; + /* a7xx+: */ struct { uint8_t ifpc_list_len; uint8_t preemption_list_len; uint16_t dynamic_list_len; }; }; - uint64_t regs[62]; + uint64_t regs[]; }; /** @@ -101,6 +103,13 @@ struct a6xx_gpu { uint64_t pwrup_reglist_iova; bool pwrup_reglist_emitted; + /* + * Offset of start of SEL regs appended to pwrup_reglist. This + * is equal to lock->dynamic_list_len if no SEL regs are appended + * to the end of the dynamic reglist. + */ + uint16_t dynamic_sel_reglist_offset; + bool has_whereami; void __iomem *llc_mmio; diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 6c040f718176..2ce7c6ac4521 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -468,6 +468,7 @@ static void a8xx_patch_pwrup_reglist(struct msm_gpu *gpu) } lock->dynamic_list_len = dyn_pwrup_reglist_count; + a6xx_gpu->dynamic_sel_reglist_offset = dyn_pwrup_reglist_count; done: a8xx_aperture_clear(gpu); -- 2.54.0