From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D339CD5BDE for ; Wed, 27 May 2026 02:44:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BC8AF10E55F; Wed, 27 May 2026 02:44:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=rock-chips.com header.i=@rock-chips.com header.b="GByMq+ar"; dkim-atps=neutral Received: from mail-m9393.xmail.ntesmail.com (mail-m9393.xmail.ntesmail.com [103.126.93.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D3A010E555 for ; Wed, 27 May 2026 02:44:33 +0000 (UTC) Received: from zyb-HP-ProDesk-680-G2-MT.. (unknown [61.154.14.86]) by smtp.qiye.163.com (Hmail) with ESMTP id 3ff559a9b; Wed, 27 May 2026 10:44:29 +0800 (GMT+08:00) From: Damon Ding To: hjc@rock-chips.com, heiko@sntech.de, andy.yan@rock-chips.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org Cc: Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, nicolas.frattaroli@collabora.com, cristian.ciocaltea@collabora.com, sebastian.reichel@collabora.com, dmitry.baryshkov@oss.qualcomm.com, luca.ceresoli@bootlin.com, dianders@chromium.org, m.szyprowski@samsung.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Damon Ding Subject: [PATCH v9 01/10] dt-bindings: display: rockchip: analogix-dp: Fix hclk as third clock for RK3588 Date: Wed, 27 May 2026 10:43:27 +0800 Message-Id: <20260527024336.191433-2-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260527024336.191433-1-damon.ding@rock-chips.com> References: <20260527024336.191433-1-damon.ding@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9e6751b89003a8kunm8053ce91bced78 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVlDTk9JVhhDThhKSkNNTRlIS1YVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSE pKQk1VSktLVUpCWQY+ DKIM-Signature: a=rsa-sha256; b=GByMq+arN60KX6irjgY72psVjPeW2E2q5n8VjeDiBp9fMfXfRQGTFCCoFpeznGzpeqeMxq5y3xxXHqJD06y5kVP8tqwvE8do3fh5U9TMleiucP4AN83aJKkSMXPJYdck150NH+FNFUrQcMvYtZ+K77FSi1hgbIqKG5HZGUjvYHc=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=JCOiC5xHahz6m4GJmafwimWE7DoGsWs8/hxxzpCEUwk=; h=date:mime-version:subject:message-id:from; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" RK3588 eDP controller requires HCLK_VO1 to access the VO1 GRF registers and enable the video datapath. Previously, the clock was enabled implicitly via the 'rockchip,vo-grf' phandle reference, which allowed the eDP to work without explicitly managing the hclk_vo1 clock. However, this is not safe or explicit. To make the clock dependency explicit, enforce per-SoC clock-names requirements: - RK3288: 2 clocks (dp, pclk) - RK3399: 3 clocks (dp, pclk, grf) - RK3588: 3 clocks (dp, pclk, hclk) Do not reuse the 'grf' clock name for RK3588 because it represents a different clock with distinct control logic: - The 'grf' clock is only for GRF register access and is toggled dynamically during register access. - The 'hclk' clock controls both GRF access and video datapath gating, and must remain enabled during probe. Fixes: f855146263b1 ("dt-bindings: display: rockchip: analogix-dp: Add support for RK3588") Signed-off-by: Damon Ding --- Changes in v4: - Modify the commit msg. Changes in v5: - Enforce the correct third clock name on a per-compatible basis. - Modify the commit msg simultaneously. Changes in v6: - Expand more detail commit msg about using hclk instead of grf clock. Changes in v7: - List all valid clock names at the top level, and constrain the clock count for each platform with minItems/maxItems in allOf. Changes in v8: - Fix indentation to 10 for enum in clock-names property. Changes in v9: - Restore the explicit clock-names for RK3399 and RK3588. --- .../rockchip/rockchip,analogix-dp.yaml | 40 ++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml index d99b23b88cc5..6643889f2a9c 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml @@ -26,7 +26,9 @@ properties: items: - const: dp - const: pclk - - const: grf + - enum: + - grf + - hclk power-domains: maxItems: 1 @@ -60,6 +62,35 @@ required: allOf: - $ref: /schemas/display/bridge/analogix,dp.yaml# + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3288-dp + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3399-edp + then: + properties: + clocks: + minItems: 3 + clock-names: + items: + - const: dp + - const: pclk + - const: grf + - if: properties: compatible: @@ -68,6 +99,13 @@ allOf: - rockchip,rk3588-edp then: properties: + clocks: + minItems: 3 + clock-names: + items: + - const: dp + - const: pclk + - const: hclk resets: minItems: 2 reset-names: -- 2.34.1