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([103.218.174.23]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-841d70b855csm1651909b3a.38.2026.05.27.01.57.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2026 01:58:00 -0700 (PDT) From: Sudarshan Shetty To: andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org Cc: Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, luca.ceresoli@bootlin.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, alexander.stein@ew.tq-group.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Sudarshan Shetty Subject: [PATCH v4 0/2] drm: bridge: ti-sn65dsi83: Fix DSI mode flags for stable LVDS output Date: Wed, 27 May 2026 14:27:34 +0530 Message-Id: <20260527085736.920390-1-tessolveupstream@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi all, This patch refines dual-link LVDS support in the SN65DSI83/84 DSI-to-LVDS bridge driver. Recent upstream changes added support for dual-link LVDS timing adjustments and related fixes: - Halving horizontal timing parameters - Test pattern handling adjustments - DSI clock range correction However, during validation on our platform, LVDS output remained unstable for certain panels due to the DSI mode configuration. Specifically, the following flags were found to cause issues: - MIPI_DSI_MODE_VIDEO_NO_HFP - MIPI_DSI_MODE_VIDEO_NO_HBP These disable transmission of horizontal front porch (HFP) and back porch (HBP) timings over the DSI link. The SN65DSI bridge relies on complete horizontal timing information to reconstruct LVDS timings, and omitting these parameters results in incorrect or unstable output. Reference: SN65DSI84 Datasheet, Section 7.4.7 (page 20): https://www.ti.com/lit/ds/symlink/sn65dsi84.pdf?ts=1776924088430&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FSN65DSI84 Additionally: - MIPI_DSI_MODE_VIDEO_BURST While supported by the hardware, burst mode operation depends on continuous clocking from the DSI host. In practice, this may lead to instability depending on the host controller implementation, as the link may transition to LP mode between bursts. Removing these flags ensures that: - Full timing information is transmitted - The bridge can correctly reconstruct LVDS timings - Output remains stable across tested panels This patch updates the DSI mode configuration accordingly. Changes in v4: - Split the original patch into two separate patches: - Enable HFP/HBP transmission by removing MIPI_DSI_MODE_VIDEO_NO_HFP and MIPI_DSI_MODE_VIDEO_NO_HBP - Disable MIPI_DSI_MODE_VIDEO_BURST separately - Updated commit messages Changes in v3: - Rebased on top of latest upstream changes - Dropped previously proposed dual-link DT property and related handling as equivalent functionality is now available upstream - Refined DSI mode flag configuration to ensure stable LVDS output - Added detailed justification for removing NO_HFP/NO_HBP and BURST mode Changes in v2: - Introduced ti,dual-link-video-mode DT property - Added DT binding documentation for the new property - Update driver to read the DT property and apply dual-link configuration conditionally - Adjust DSI mode flags when dual-link video mode is enabled - Update commit messages Thanks, Anusha Sudarshan Shetty (2): drm: bridge: ti-sn65dsi83: Remove NO_HFP and NO_HBP mode flags for LVDS stability drm: bridge: ti-sn65dsi83: Disable video burst mode for LVDS stability drivers/gpu/drm/bridge/ti-sn65dsi83.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.34.1