From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09B98CD6E45 for ; Wed, 27 May 2026 11:12:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 04CD710E79C; Wed, 27 May 2026 11:12:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ifD3hyAR"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id A5E9E10E78D; Wed, 27 May 2026 11:12:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779880360; x=1811416360; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T/lCvgVFpvLp9yGiGIWrtht79D66gSCOzOaAwFziY8I=; b=ifD3hyARZSKefVh1M7bkr/e8VNvN26xFBVI97Tj70VEVh2uHhr2KOTDZ PlK5gP24pYowvVEZr8LMpmWtPBigLRIcrwfHXsxqp2qShG/qZXErPSDir AvnMwe+WBsFAUE5pEFFKxzmc9cIJoj3dclOqkNbsSZ62Cd/oe4kXK9kXo Tq4XF5eplrjUpa36AwDpfCYVVEUcLvhpD76wrjxMZa55ddULYX5+ylOVd 5a+wZsh5FC35L1IPBqm7SANvnoggdUgwZSk526gf1Oat4bsZncERg4IhF Bs4zvc/Au2dVVkOd8bXxWvSqxEPHgURpjnnG2eEFJ68W90FYlLby2pfd1 g==; X-CSE-ConnectionGUID: 0sdF8LByTneMQKJaWcdYmA== X-CSE-MsgGUID: RqI5bC7iTwmfo4Vgaq+Okw== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="80818517" X-IronPort-AV: E=Sophos;i="6.24,171,1774335600"; d="scan'208";a="80818517" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2026 04:12:40 -0700 X-CSE-ConnectionGUID: KlpykEDSQCSTmNYFP0GbXw== X-CSE-MsgGUID: rOKDYCKIQpytrFdmZiXEIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,171,1774335600"; d="scan'208";a="265803175" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa002.fm.intel.com with ESMTP; 27 May 2026 04:12:38 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 3/4] drm/dp: Add max bpp delta computation constants Date: Wed, 27 May 2026 16:38:48 +0530 Message-Id: <20260527110849.3943338-4-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260527110849.3943338-1-nemesa.garg@intel.com> References: <20260527110849.3943338-1-nemesa.garg@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Define macros used for decoding DSC max bpp delta values from the sink DPCD. This includes per-format masks for RGB/YCbCr444 and YCbCr420, as well as definitions for delta scaling and the YCbCr420 bit shift. Also add version_1 as suffix to MAX_DELTA_BPP. v2: Move constants under 0x6E register. [Ankit] Add mask for Native 422 also. [Ankit] v3: Rename _DSC_NATIVE4222 to _DSC_NATIVE_YCbCr422. [Ankit] Signed-off-by: Nemesa Garg --- include/drm/display/drm_dp.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index dce290acf735..a905aa49d1d0 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -354,10 +354,14 @@ # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1) # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) -#define DP_DSC_MAX_BPP_DELTA 0x06E +#define DP_DSC_MAX_BPP_DELTA_VERSION_1 0x06E # define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f # define DP_DSC_NATIVE_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 +# define DP_DSC_BPP_DELTA_444 16 +# define DP_DSC_BPP_DELTA_420 12 +# define DP_DSC_BPP_DELTA_SHIFT_420 5 + #define DP_DSC_BITS_PER_PIXEL_INC 0x06F # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 @@ -365,6 +369,8 @@ # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 # define DP_DSC_BITS_PER_PIXEL_1_1 0x4 # define DP_DSC_BITS_PER_PIXEL_MASK 0x7 +# define DP_DSC_NATIVE_YCbCr422_MAX_BPP_DELTA_MASK 0x78 +# define DP_DSC_BPP_DELTA_NATIVE_422 16 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 -- 2.25.1