From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A9EDCD6E4C for ; Fri, 29 May 2026 08:47:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EED5B10FB0D; Fri, 29 May 2026 08:47:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="i6bYvpr/"; dkim-atps=neutral Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9165F10FB03 for ; Fri, 29 May 2026 08:47:21 +0000 (UTC) Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 84D7A20F9; Fri, 29 May 2026 10:46:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1780044420; bh=uYpBzCI5/EIYS0A0eORGLebFKyluSlYajSBf8Czw3RM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=i6bYvpr/Wh5Ll82dXtpjLWBx8b6W8KAMX/VhGN/qqqix/6bfkDFXqUty5auM0dml6 9mWdOCaCiBVtu+2I01wl+1/Ose5sio6fTvlG5hzvYp1e2ZQ5SSL6PyUqeHgPebx7fX 1N1ib0JYuQ4JgeJmkYKhfECGYck04E0hSrwhuRSA= From: Tomi Valkeinen Date: Fri, 29 May 2026 11:45:35 +0300 Subject: [PATCH v3 05/15] dt-bindings: display: ti,am65x-dss: Add AM62P DSS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260529-beagley-ai-display-v3-5-7fefdc5d1adf@ideasonboard.com> References: <20260529-beagley-ai-display-v3-0-7fefdc5d1adf@ideasonboard.com> In-Reply-To: <20260529-beagley-ai-display-v3-0-7fefdc5d1adf@ideasonboard.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Aradhya Bhatia , Nishanth Menon , Vignesh Raghavendra , Swamil Jain , Devarsh Thakkar , Louis Chauvet Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tomi Valkeinen X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3512; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=uYpBzCI5/EIYS0A0eORGLebFKyluSlYajSBf8Czw3RM=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBqGVKMbB14c2XE4t0f3oamTKKmG1ZiaLbx/63K6 6XxG0PYyuCJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCahlSjAAKCRD6PaqMvJYe 9cs2D/9b/3lUX5/1QkZrCDXNlrtP/DySHlPixDNAkXipv7uOfcugtM8KbX5QJFkdTZ1aoJdpSzP lcXWyYBuwqK4ju0rflXnOEgqgZUVh6OVbP0qLNZVcJ2Fb1ONCxp0zmPD5d+22hUB80mSdvca3lC rcvDUJTGjGE77wCvkJ0vw4Y6rO1C7X9d4C2gEU37E8JlujuDe9YyzkW0vKY5GM4lIgk6+hKuTZy h3jXCZ8P2ssggJr0cPeo37W1iqkkuZJFJGdT2RjGWtotHTsXgGTxs/WMMgyc6ukBp2wYRUjK7xR P38oLzDOyPreyYKi9PqZhKP+A/UsC2yVeCiAV82ebQJnCI9FAII86PA1BxJmo5fXFq6YeUA3ohL 5sT5D2AMSgy5JgoDX90dNmINHQphONRqFLx7CoSCIZ4wGiFv/WmY4jb+C2jhJHvCHlwNA3P4ay8 f4PpUOU6IGMiQRCxxFclFOJLaO0SR5uzEkCJbCMKwYGzF8n+3sr6O3UxsH2QgFxMppK3Jf7Sq/Z qAit7SjO+vIez781FSqOSOeH8BDP3Hi/I+TfglX4jfPx2i0gwsWnyOWaqqY8cYYHXgqwGrWGXdl vgGO8fVo0URNsylI5qsvzBNA9l735d3T3PycHku7TLyqYlDqY5lgSqIYkK5IRBVKKepQk6E91Iy J+deiWB1yjnUVgQ== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" TI's AM62P, J722S and AM67A SoCs contain same implementation of the display subsystem (DSS). There are two instances of the DSS (DSS0 and DSS1), each with two video ports (VP) and two video planes. Additionally the SoCs contain two OLDI TXes (OLDI0 and OLDI1), a MIPI DSI TX and a MIPI DPI output path. DSS0 supports: - VP0: OLDI0 in single-link mode, or OLDI0 and OLDI1 in dual-link or clone mode. - VP1: DPI DSS1 supports: - VP0: OLDI1 in single-link mode, or DPI - VP1: DPI or DSI The DSI is only connected to VP1 of DSS1, but OLDI and DPI are shared between the DSS instances. Thus only a single VP can output to DPI, and a single VP can use an OLDI block. Note that in single-link configuration OLDI0 can be used by DSS0, and at the same time OLDI1 can be used by DSS1. The DSS IP itself is compatible with older SoCs. While we could use "ti,am625-dss" compatible string, we add a new one "ti,am62p-dss" to be on the safe side in case the driver needs to do something special for the dual-DSS case in the future. Original patch by Swamil Jain Reviewed-by: Rob Herring (Arm) Signed-off-by: Tomi Valkeinen --- .../bindings/display/ti/ti,am65x-dss.yaml | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 902ae2122d86..acb7ac635097 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -28,11 +28,38 @@ description: | On AM62A7, the first VP is tied off in the SoC, and the second VP is routed to external MIPI DPI pins. + AM62P SoC contains two instances of the DSS: + On AM62P DSS0, the first VP is connected to two OLDI TX instances (the second + TX shared with DSS1), the second VP to external MIPI DPI pins (shared with + DSS1). + On AM62P DSS1, the first VP is connected either to the second OLDI TX, or + external MIPI DPI pins. The second VP is connected to either the external MIPI + DPI pins or a Cadence DSI TX. + + An important note about OLDIs on AM62P: + + There are two OLDI hardware blocks. Each OLDI has certain configuration that + has to be done before it can be used. The OLDI blocks get this configuration + directly from the DSS block, via DSS registers. However, as a single OLDI + block can be used either with DSS0 or DSS1, the source for the configuration + changes according to a mux. This mux is set according to the OLDI + configuration registers in DSS0. Thus the OLDI control paths change at + runtime, and it is not obvious how to structure this in the DT bindings. + + The solution used here is that each DSS node contains the OLDI nodes that can + be used with that DSS. Thus the DSS0 node has two OLDI child nodes, OLDI0 and + OLDI1, and the DSS1 node has one OLDI child node, OLDI1, so three OLDI DT + nodes in total. The two OLDI1 nodes thus refer to the same piece of hardware, + and they cannot be used at the same time. The selection which OLDI nodes to + use are chosen in the board dts files, so assuming the dts files are correct, + no resource conflict can happen. + properties: compatible: enum: - ti,am625-dss - ti,am62a7-dss + - ti,am62p-dss - ti,am65x-dss reg: -- 2.43.0