From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07B21CD6E69 for ; Mon, 1 Jun 2026 22:45:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 541B810FA6F; Mon, 1 Jun 2026 22:45:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=collabora.com header.i=@collabora.com header.b="ZT1SQI09"; dkim-atps=neutral Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8454C113780 for ; Mon, 1 Jun 2026 22:45:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1780353926; bh=rLAf+mCXah0GMXLUQeSkJBx6Xl8UV5ety5SsdwICkGE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZT1SQI09CvE5fZOE6CCZpC8kszlXSJN0rVL/9zcxqeAKm6KzIsWktLyDae1oDen30 vvjjxGYHqYJ0B1p5BmK4OZq0Cg4IgXa5Rk9D67pl5PlL3sqXKqJWiekRfpqzg1G9wS MHjYZVqQY/SUzlh8ecbVSuoY+LyxLROXrYrkpKS6/70VGt4XKZF3upypkFXphruF/Y t1T+GeMi2Wi7dJAC28Hp5dKnAMVe8O4MJLhns9wV2LqE4702X0q7FbHowDxDyHABxP jCC3l9T5z/x1Z1HI/SPNegAhF/M1Xz27oY2DmCSTZtn5oo0LHQ1RwXaSDU1KG0xKlC Fv4FKoeXALUiw== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 3015117E045E; Tue, 2 Jun 2026 00:45:26 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 02 Jun 2026 01:44:21 +0300 Subject: [PATCH v7 21/30] drm/rockchip: dw_hdmi_qp: Implement .{enable|disable}_hpd() PHY ops MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260602-dw-hdmi-qp-scramb-v7-21-445eb54ee1ed@collabora.com> References: <20260602-dw-hdmi-qp-scramb-v7-0-445eb54ee1ed@collabora.com> In-Reply-To: <20260602-dw-hdmi-qp-scramb-v7-0-445eb54ee1ed@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Daniel Stone , Dave Stevenson , =?utf-8?q?Ma=C3=ADra_Canal?= , Raspberry Pi Kernel Maintenance Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.15.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement .enable_hpd() and .disable_hpd() phy ops for RK3576 and RK3588 SoCs, used by the corresponding bridge callbacks for HPD activation control. Consolidate the interrupt clear-and-unmask sequence into enable_hpd() and the mask-only operation into disable_hpd(), replacing the open-coded register writes in the interrupt handlers and io_init(). The .setup_hpd() phy op, which was previously called from dw_hdmi_qp_init_hw(), is no longer needed and its users are removed. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 78 +++++++++++++------------- 1 file changed, 38 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c index 62ea5c7cbbe6..b9e0ea56efd8 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -193,7 +193,7 @@ dw_hdmi_qp_rk3588_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) return val ? connector_status_connected : connector_status_disconnected; } -static void dw_hdmi_qp_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +static void dw_hdmi_qp_rk3588_enable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) { struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; u32 val; @@ -208,11 +208,25 @@ static void dw_hdmi_qp_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); } +static void dw_hdmi_qp_rk3588_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +{ + struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + u32 val; + + if (hdmi->port_id) + val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1); + else + val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1); + + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); +} + static const struct dw_hdmi_qp_phy_ops rk3588_hdmi_phy_ops = { .init = dw_hdmi_qp_rk3588_phy_init, .disable = dw_hdmi_qp_rk3588_phy_disable, .read_hpd = dw_hdmi_qp_rk3588_read_hpd, - .setup_hpd = dw_hdmi_qp_rk3588_setup_hpd, + .enable_hpd = dw_hdmi_qp_rk3588_enable_hpd, + .disable_hpd = dw_hdmi_qp_rk3588_disable_hpd, }; static enum drm_connector_status @@ -227,7 +241,7 @@ dw_hdmi_qp_rk3576_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) connector_status_connected : connector_status_disconnected; } -static void dw_hdmi_qp_rk3576_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +static void dw_hdmi_qp_rk3576_enable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) { struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; u32 val; @@ -236,14 +250,22 @@ static void dw_hdmi_qp_rk3576_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0)); regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val); - regmap_write(hdmi->regmap, 0xa404, 0xffff0102); +} + +static void dw_hdmi_qp_rk3576_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +{ + struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + + regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, + FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1)); } static const struct dw_hdmi_qp_phy_ops rk3576_hdmi_phy_ops = { .init = dw_hdmi_qp_rk3588_phy_init, .disable = dw_hdmi_qp_rk3588_phy_disable, .read_hpd = dw_hdmi_qp_rk3576_read_hpd, - .setup_hpd = dw_hdmi_qp_rk3576_setup_hpd, + .enable_hpd = dw_hdmi_qp_rk3576_enable_hpd, + .disable_hpd = dw_hdmi_qp_rk3576_disable_hpd, }; static void dw_hdmi_qp_rk3588_hpd_work(struct work_struct *work) @@ -264,13 +286,12 @@ static void dw_hdmi_qp_rk3588_hpd_work(struct work_struct *work) static irqreturn_t dw_hdmi_qp_rk3576_hardirq(int irq, void *dev_id) { struct rockchip_hdmi_qp *hdmi = dev_id; - u32 intr_stat, val; + u32 intr_stat; regmap_read(hdmi->regmap, RK3576_IOC_HDMI_HPD_STATUS, &intr_stat); - if (intr_stat) { - val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1); - regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val); + if (intr_stat) { + dw_hdmi_qp_rk3576_disable_hpd(NULL, hdmi); return IRQ_WAKE_THREAD; } @@ -280,15 +301,11 @@ static irqreturn_t dw_hdmi_qp_rk3576_hardirq(int irq, void *dev_id) static irqreturn_t dw_hdmi_qp_rk3576_irq(int irq, void *dev_id) { struct rockchip_hdmi_qp *hdmi = dev_id; - u32 val; - val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1); - regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val); mod_delayed_work(system_percpu_wq, &hdmi->hpd_work, msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); - val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0); - regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val); + dw_hdmi_qp_rk3576_enable_hpd(NULL, hdmi); return IRQ_HANDLED; } @@ -296,16 +313,12 @@ static irqreturn_t dw_hdmi_qp_rk3576_irq(int irq, void *dev_id) static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id) { struct rockchip_hdmi_qp *hdmi = dev_id; - u32 intr_stat, val; + u32 intr_stat; regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); if (intr_stat) { - if (hdmi->port_id) - val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1); - else - val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1); - regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + dw_hdmi_qp_rk3588_disable_hpd(NULL, hdmi); return IRQ_WAKE_THREAD; } @@ -315,22 +328,11 @@ static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id) static irqreturn_t dw_hdmi_qp_rk3588_irq(int irq, void *dev_id) { struct rockchip_hdmi_qp *hdmi = dev_id; - u32 val; - - if (hdmi->port_id) - val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_CLR, 1); - else - val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_CLR, 1); - regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); mod_delayed_work(system_percpu_wq, &hdmi->hpd_work, msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); - if (hdmi->port_id) - val |= FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 0); - else - val |= FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 0); - regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + dw_hdmi_qp_rk3588_enable_hpd(NULL, hdmi); return IRQ_HANDLED; } @@ -343,11 +345,11 @@ static void dw_hdmi_qp_rk3576_io_init(struct rockchip_hdmi_qp *hdmi) FIELD_PREP_WM16(RK3576_SDAIN_MASK, 1) | FIELD_PREP_WM16(RK3576_HDMI_GRANT_SEL, 1) | FIELD_PREP_WM16(RK3576_I2S_SEL_MASK, 1); - regmap_write(hdmi->vo_regmap, RK3576_VO0_GRF_SOC_CON14, val); - val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1); - regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val); + regmap_write(hdmi->regmap, 0xa404, 0xffff0102); + + dw_hdmi_qp_rk3576_disable_hpd(NULL, hdmi); } static void dw_hdmi_qp_rk3588_io_init(struct rockchip_hdmi_qp *hdmi) @@ -372,11 +374,7 @@ static void dw_hdmi_qp_rk3588_io_init(struct rockchip_hdmi_qp *hdmi) val = FIELD_PREP_WM16(RK3588_HDMI0_GRANT_SEL, 1); regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val); - if (hdmi->port_id) - val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1); - else - val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1); - regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + dw_hdmi_qp_rk3588_disable_hpd(NULL, hdmi); } static void dw_hdmi_qp_rk3576_enc_init(struct rockchip_hdmi_qp *hdmi, -- 2.54.0