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d="scan'208";a="240162126" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by fmviesa006.fm.intel.com with ESMTP; 04 Jun 2026 11:53:11 -0700 From: Raag Jadav To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, netdev@vger.kernel.org Cc: simona.vetter@ffwll.ch, airlied@gmail.com, kuba@kernel.org, lijo.lazar@amd.com, Hawking.Zhang@amd.com, davem@davemloft.net, pabeni@redhat.com, edumazet@google.com, dev@lankhorst.se, zachary.mckevitt@oss.qualcomm.com, rodrigo.vivi@intel.com, riana.tauro@intel.com, michal.wajdeczko@intel.com, matthew.d.roper@intel.com, mallesh.koujalagi@intel.com, Raag Jadav Subject: [PATCH v3 4/4] drm/xe/drm_ras: Wire up error threshold callbacks Date: Fri, 5 Jun 2026 00:16:43 +0530 Message-ID: <20260604184849.1011985-5-raag.jadav@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260604184849.1011985-1-raag.jadav@intel.com> References: <20260604184849.1011985-1-raag.jadav@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Now that we have get/set error threshold support in xe driver, wire them up to drm_ras so that userspace can make use of the functionality. $ sudo ynl --family drm_ras --do get-error-threshold \ --json '{"node-id":0, "error-id":2}' {'error-id': 2, 'error-name': 'soc-internal', 'error-threshold': 16} $ sudo ynl --family drm_ras --do set-error-threshold \ --json '{"node-id":0, "error-id":2, "error-threshold":8}' None Signed-off-by: Raag Jadav Reviewed-by: Riana Tauro --- v3: Return -ENOENT on info absence (Riana) --- drivers/gpu/drm/xe/xe_drm_ras.c | 34 +++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_drm_ras.c b/drivers/gpu/drm/xe/xe_drm_ras.c index 7937d8ba0ed9..24e5082add37 100644 --- a/drivers/gpu/drm/xe/xe_drm_ras.c +++ b/drivers/gpu/drm/xe/xe_drm_ras.c @@ -86,6 +86,38 @@ static int clear_correctable_error_counter(struct drm_ras_node *node, u32 error_ return clear_error_counter(xe, DRM_XE_RAS_ERR_SEV_CORRECTABLE, error_id); } +static int query_correctable_error_threshold(struct drm_ras_node *ep, u32 error_id, + const char **name, u32 *val) +{ + struct xe_device *xe = ep->priv; + struct xe_drm_ras *ras = &xe->ras; + struct xe_drm_ras_counter *info = ras->info[DRM_XE_RAS_ERR_SEV_CORRECTABLE]; + + if (!info || !info[error_id].name) + return -ENOENT; + + if (!xe->info.has_sysctrl) + return -EOPNOTSUPP; + + *name = info[error_id].name; + return xe_ras_get_threshold(xe, DRM_XE_RAS_ERR_SEV_CORRECTABLE, error_id, val); +} + +static int set_correctable_error_threshold(struct drm_ras_node *ep, u32 error_id, u32 val) +{ + struct xe_device *xe = ep->priv; + struct xe_drm_ras *ras = &xe->ras; + struct xe_drm_ras_counter *info = ras->info[DRM_XE_RAS_ERR_SEV_CORRECTABLE]; + + if (!info || !info[error_id].name) + return -ENOENT; + + if (!xe->info.has_sysctrl) + return -EOPNOTSUPP; + + return xe_ras_set_threshold(xe, DRM_XE_RAS_ERR_SEV_CORRECTABLE, error_id, val); +} + static struct xe_drm_ras_counter *allocate_and_copy_counters(struct xe_device *xe) { struct xe_drm_ras_counter *counter; @@ -134,6 +166,8 @@ static int assign_node_params(struct xe_device *xe, struct drm_ras_node *node, if (severity == DRM_XE_RAS_ERR_SEV_CORRECTABLE) { node->query_error_counter = query_correctable_error_counter; node->clear_error_counter = clear_correctable_error_counter; + node->query_error_threshold = query_correctable_error_threshold; + node->set_error_threshold = set_correctable_error_threshold; } else { node->query_error_counter = query_uncorrectable_error_counter; node->clear_error_counter = clear_uncorrectable_error_counter; -- 2.43.0