[PATCH v7 0/3] Panel Replay BW optimization

[PATCH v7 0/3] Panel Replay BW optimization

[Animesh Manna]

Unused bandwidth can be used by external display agents for Panel Replay
enabled DP panel during idleness with link on. This patch series
enabling the same.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Animesh Manna (3):
  drm/i915/display: Add drm helper to check pr optimization support
  drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling
  drm/i915/display: Disable Panel Replay for DP-tunneling without
    optimization

 drivers/gpu/drm/display/drm_dp_tunnel.c       | 17 ++++++++++
 .../gpu/drm/i915/display/intel_display_regs.h |  1 +
 .../gpu/drm/i915/display/intel_dp_tunnel.c    | 14 +++++++++
 .../gpu/drm/i915/display/intel_dp_tunnel.h    |  6 ++++
 drivers/gpu/drm/i915/display/intel_psr.c      | 31 +++++++++++++++++--
 include/drm/display/drm_dp_tunnel.h           |  6 ++++
 6 files changed, 73 insertions(+), 2 deletions(-)

-- 
2.29.0

[PATCH v7 1/3] drm/i915/display: Add drm helper to check pr optimization support

[Animesh Manna]

Add api to check panel replay optimization supported or not to
drm-core DP tunneling framework which can be used by other driver
as well.

Suggested-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/display/drm_dp_tunnel.c        | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp_tunnel.h |  6 ++++++
 include/drm/display/drm_dp_tunnel.h            |  6 ++++++
 4 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_tunnel.c b/drivers/gpu/drm/display/drm_dp_tunnel.c
index f442430d8de7..39c07cb4123b 100644
--- a/drivers/gpu/drm/display/drm_dp_tunnel.c
+++ b/drivers/gpu/drm/display/drm_dp_tunnel.c
@@ -149,6 +149,7 @@ struct drm_dp_tunnel {
 	bool bw_alloc_enabled:1;
 	bool has_io_error:1;
 	bool destroyed:1;
+	bool pr_optimization_support:1;
 };
 
 struct drm_dp_tunnel_group_state;
@@ -508,6 +509,8 @@ create_tunnel(struct drm_dp_tunnel_mgr *mgr,
 
 	tunnel->bw_alloc_supported = tunnel_reg_bw_alloc_supported(regs);
 	tunnel->bw_alloc_enabled = tunnel_reg_bw_alloc_enabled(regs);
+	tunnel->pr_optimization_support = tunnel_reg(regs, DP_TUNNELING_CAPABILITIES) &
+					  DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT;
 
 	if (!add_tunnel_to_group(mgr, drv_group_id, tunnel)) {
 		kfree(tunnel);
@@ -1036,6 +1039,20 @@ bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel)
 }
 EXPORT_SYMBOL(drm_dp_tunnel_bw_alloc_is_enabled);
 
+/**
+ * drm_dp_tunnel_pr_optimization_supported - Query the PR BW optimization support
+ * @tunnel: Tunnel object
+ *
+ * Query if the PR BW optimization is supported for @tunnel.
+ *
+ * Returns %true if the PR BW optimiation is supported for @tunnel.
+ */
+bool drm_dp_tunnel_pr_optimization_supported(const struct drm_dp_tunnel *tunnel)
+{
+	return tunnel && tunnel->pr_optimization_support;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_pr_optimization_supported);
+
 static int clear_bw_req_state(struct drm_dp_aux *aux)
 {
 	u8 bw_req_mask = DP_BW_REQUEST_SUCCEEDED | DP_BW_REQUEST_FAILED;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
index 1fd1ac8d556d..075aea9d6ede 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
@@ -296,6 +296,20 @@ bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp)
 	return drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel);
 }
 
+/**
+ * intel_dp_tunnel_pr_optimization_supported - Query the PR BW optimization support
+ * @intel_dp: DP port object
+ *
+ * Query whether a DP tunnel is connected on @intel_dp and the tunnel supports
+ * the PR BW optimization.
+ *
+ * Returns %true if the BW allocation mode is supported on @intel_dp.
+ */
+bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp)
+{
+	return drm_dp_tunnel_pr_optimization_supported(intel_dp->tunnel);
+}
+
 /**
  * intel_dp_tunnel_suspend - Suspend a DP tunnel connected on a port
  * @intel_dp: DP port object
diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
index 7f0f720e8dca..03e147736b65 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
@@ -32,6 +32,7 @@ void intel_dp_tunnel_resume(struct intel_dp *intel_dp,
 void intel_dp_tunnel_suspend(struct intel_dp *intel_dp);
 
 bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp);
+bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp);
 
 void
 intel_dp_tunnel_atomic_cleanup_inherited_state(struct intel_atomic_state *state);
@@ -76,6 +77,11 @@ static inline bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp
 	return false;
 }
 
+static inline bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp)
+{
+	return false;
+}
+
 static inline void
 intel_dp_tunnel_atomic_cleanup_inherited_state(struct intel_atomic_state *state) {}
 
diff --git a/include/drm/display/drm_dp_tunnel.h b/include/drm/display/drm_dp_tunnel.h
index 87212c847915..4aa3ce9fd829 100644
--- a/include/drm/display/drm_dp_tunnel.h
+++ b/include/drm/display/drm_dp_tunnel.h
@@ -53,6 +53,7 @@ int drm_dp_tunnel_destroy(struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel);
 bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel);
+bool drm_dp_tunnel_pr_optimization_supported(const struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw);
 int drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel);
@@ -140,6 +141,11 @@ static inline bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel
 	return false;
 }
 
+static inline bool drm_dp_tunnel_pr_optimization_supported(const struct drm_dp_tunnel *tunnel)
+{
+	return false;
+}
+
 static inline int
 drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw)
 {
-- 
2.29.0

Re: [PATCH v7 1/3] drm/i915/display: Add drm helper to check pr optimization support

[Hogander, Jouni]

On Thu, 2026-03-12 at 10:30 +0530, Animesh Manna wrote:
> Add api to check panel replay optimization supported or not to
> drm-core DP tunneling framework which can be used by other driver
> as well.
> 
> Suggested-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/display/drm_dp_tunnel.c        | 17
> +++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 14 ++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp_tunnel.h |  6 ++++++
>  include/drm/display/drm_dp_tunnel.h            |  6 ++++++
>  4 files changed, 43 insertions(+)
> 
> diff --git a/drivers/gpu/drm/display/drm_dp_tunnel.c
> b/drivers/gpu/drm/display/drm_dp_tunnel.c
> index f442430d8de7..39c07cb4123b 100644
> --- a/drivers/gpu/drm/display/drm_dp_tunnel.c
> +++ b/drivers/gpu/drm/display/drm_dp_tunnel.c
> @@ -149,6 +149,7 @@ struct drm_dp_tunnel {
>  	bool bw_alloc_enabled:1;
>  	bool has_io_error:1;
>  	bool destroyed:1;
> +	bool pr_optimization_support:1;
>  };
>  
>  struct drm_dp_tunnel_group_state;
> @@ -508,6 +509,8 @@ create_tunnel(struct drm_dp_tunnel_mgr *mgr,
>  
>  	tunnel->bw_alloc_supported =
> tunnel_reg_bw_alloc_supported(regs);
>  	tunnel->bw_alloc_enabled =
> tunnel_reg_bw_alloc_enabled(regs);
> +	tunnel->pr_optimization_support = tunnel_reg(regs,
> DP_TUNNELING_CAPABILITIES) &
> +					 
> DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT;
>  
>  	if (!add_tunnel_to_group(mgr, drv_group_id, tunnel)) {
>  		kfree(tunnel);
> @@ -1036,6 +1039,20 @@ bool drm_dp_tunnel_bw_alloc_is_enabled(const
> struct drm_dp_tunnel *tunnel)
>  }
>  EXPORT_SYMBOL(drm_dp_tunnel_bw_alloc_is_enabled);
>  
> +/**
> + * drm_dp_tunnel_pr_optimization_supported - Query the PR BW
> optimization support
> + * @tunnel: Tunnel object
> + *
> + * Query if the PR BW optimization is supported for @tunnel.
> + *
> + * Returns %true if the PR BW optimiation is supported for @tunnel.
> + */
> +bool drm_dp_tunnel_pr_optimization_supported(const struct
> drm_dp_tunnel *tunnel)
> +{
> +	return tunnel && tunnel->pr_optimization_support;
> +}
> +EXPORT_SYMBOL(drm_dp_tunnel_pr_optimization_supported);
> +
>  static int clear_bw_req_state(struct drm_dp_aux *aux)
>  {
>  	u8 bw_req_mask = DP_BW_REQUEST_SUCCEEDED |
> DP_BW_REQUEST_FAILED;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> index 1fd1ac8d556d..075aea9d6ede 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> @@ -296,6 +296,20 @@ bool intel_dp_tunnel_bw_alloc_is_enabled(struct
> intel_dp *intel_dp)
>  	return drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel);
>  }
>  
> +/**
> + * intel_dp_tunnel_pr_optimization_supported - Query the PR BW
> optimization support
> + * @intel_dp: DP port object
> + *
> + * Query whether a DP tunnel is connected on @intel_dp and the
> tunnel supports
> + * the PR BW optimization.

How this is checking if DP tunnel is connected? To me it looks like it
is just checking if PR BW optimization is supported.

> + *
> + * Returns %true if the BW allocation mode is supported on
> @intel_dp.
> + */
> +bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp
> *intel_dp)
> +{
> +	return drm_dp_tunnel_pr_optimization_supported(intel_dp-
> >tunnel);
> +}

I would guess it is not ok to mix Intel specific and generic drm
changes into one patch.

Maybe you could add:

if (DISPLAY_VER(display) < 35)
	return false;

into here? Otherwise you need to modify check in patch 3 as:

if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp) &&
    (DISPLAY_VER(display) < 35 ||
     !intel_dp_tunnel_pr_optimization_supported(intel_dp)))
    
	   BR,
Jouni Högander

> +
>  /**
>   * intel_dp_tunnel_suspend - Suspend a DP tunnel connected on a port
>   * @intel_dp: DP port object
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> index 7f0f720e8dca..03e147736b65 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> @@ -32,6 +32,7 @@ void intel_dp_tunnel_resume(struct intel_dp
> *intel_dp,
>  void intel_dp_tunnel_suspend(struct intel_dp *intel_dp);
>  
>  bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp);
> +bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp
> *intel_dp);
>  
>  void
>  intel_dp_tunnel_atomic_cleanup_inherited_state(struct
> intel_atomic_state *state);
> @@ -76,6 +77,11 @@ static inline bool
> intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp
>  	return false;
>  }
>  
> +static inline bool intel_dp_tunnel_pr_optimization_supported(struct
> intel_dp *intel_dp)
> +{
> +	return false;
> +}
> +
>  static inline void
>  intel_dp_tunnel_atomic_cleanup_inherited_state(struct
> intel_atomic_state *state) {}
>  
> diff --git a/include/drm/display/drm_dp_tunnel.h
> b/include/drm/display/drm_dp_tunnel.h
> index 87212c847915..4aa3ce9fd829 100644
> --- a/include/drm/display/drm_dp_tunnel.h
> +++ b/include/drm/display/drm_dp_tunnel.h
> @@ -53,6 +53,7 @@ int drm_dp_tunnel_destroy(struct drm_dp_tunnel
> *tunnel);
>  int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel);
>  int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel);
>  bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel
> *tunnel);
> +bool drm_dp_tunnel_pr_optimization_supported(const struct
> drm_dp_tunnel *tunnel);
>  int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw);
>  int drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel);
>  int drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel);
> @@ -140,6 +141,11 @@ static inline bool
> drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel
>  	return false;
>  }
>  
> +static inline bool drm_dp_tunnel_pr_optimization_supported(const
> struct drm_dp_tunnel *tunnel)
> +{
> +	return false;
> +}
> +
>  static inline int
>  drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw)
>  {

RE: [PATCH v7 1/3] drm/i915/display: Add drm helper to check pr optimization support

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Thursday, March 12, 2026 12:10 PM
> To: intel-xe@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Manna,
> Animesh <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Deak, Imre <imre.deak@intel.com>
> Subject: Re: [PATCH v7 1/3] drm/i915/display: Add drm helper to check pr
> optimization support
> 
> On Thu, 2026-03-12 at 10:30 +0530, Animesh Manna wrote:
> > Add api to check panel replay optimization supported or not to
> > drm-core DP tunneling framework which can be used by other driver as
> > well.
> >
> > Suggested-by: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/display/drm_dp_tunnel.c        | 17
> > +++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 14 ++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_dp_tunnel.h |  6 ++++++
> >  include/drm/display/drm_dp_tunnel.h            |  6 ++++++
> >  4 files changed, 43 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dp_tunnel.c
> > b/drivers/gpu/drm/display/drm_dp_tunnel.c
> > index f442430d8de7..39c07cb4123b 100644
> > --- a/drivers/gpu/drm/display/drm_dp_tunnel.c
> > +++ b/drivers/gpu/drm/display/drm_dp_tunnel.c
> > @@ -149,6 +149,7 @@ struct drm_dp_tunnel {
> >  	bool bw_alloc_enabled:1;
> >  	bool has_io_error:1;
> >  	bool destroyed:1;
> > +	bool pr_optimization_support:1;
> >  };
> >
> >  struct drm_dp_tunnel_group_state;
> > @@ -508,6 +509,8 @@ create_tunnel(struct drm_dp_tunnel_mgr *mgr,
> >
> >  	tunnel->bw_alloc_supported =
> > tunnel_reg_bw_alloc_supported(regs);
> >  	tunnel->bw_alloc_enabled =
> > tunnel_reg_bw_alloc_enabled(regs);
> > +	tunnel->pr_optimization_support = tunnel_reg(regs,
> > DP_TUNNELING_CAPABILITIES) &
> > +
> > DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT;
> >
> >  	if (!add_tunnel_to_group(mgr, drv_group_id, tunnel)) {
> >  		kfree(tunnel);
> > @@ -1036,6 +1039,20 @@ bool
> drm_dp_tunnel_bw_alloc_is_enabled(const
> > struct drm_dp_tunnel *tunnel)
> >  }
> >  EXPORT_SYMBOL(drm_dp_tunnel_bw_alloc_is_enabled);
> >
> > +/**
> > + * drm_dp_tunnel_pr_optimization_supported - Query the PR BW
> > optimization support
> > + * @tunnel: Tunnel object
> > + *
> > + * Query if the PR BW optimization is supported for @tunnel.
> > + *
> > + * Returns %true if the PR BW optimiation is supported for @tunnel.
> > + */
> > +bool drm_dp_tunnel_pr_optimization_supported(const struct
> > drm_dp_tunnel *tunnel)
> > +{
> > +	return tunnel && tunnel->pr_optimization_support; }
> > +EXPORT_SYMBOL(drm_dp_tunnel_pr_optimization_supported);
> > +
> >  static int clear_bw_req_state(struct drm_dp_aux *aux)
> >  {
> >  	u8 bw_req_mask = DP_BW_REQUEST_SUCCEEDED |
> DP_BW_REQUEST_FAILED;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > index 1fd1ac8d556d..075aea9d6ede 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > @@ -296,6 +296,20 @@ bool intel_dp_tunnel_bw_alloc_is_enabled(struct
> > intel_dp *intel_dp)
> >  	return drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel);
> >  }
> >
> > +/**
> > + * intel_dp_tunnel_pr_optimization_supported - Query the PR BW
> > optimization support
> > + * @intel_dp: DP port object
> > + *
> > + * Query whether a DP tunnel is connected on @intel_dp and the
> > tunnel supports
> > + * the PR BW optimization.
> 
> How this is checking if DP tunnel is connected? To me it looks like it is just
> checking if PR BW optimization is supported.
> 
> > + *
> > + * Returns %true if the BW allocation mode is supported on
> > @intel_dp.
> > + */
> > +bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp
> > *intel_dp)
> > +{
> > +	return drm_dp_tunnel_pr_optimization_supported(intel_dp-
> > >tunnel);
> > +}
> 
> I would guess it is not ok to mix Intel specific and generic drm changes into
> one patch.

Sure, will split in different patch.

> 
> Maybe you could add:
> 
> if (DISPLAY_VER(display) < 35)
> 	return false;
> 
> into here? Otherwise you need to modify check in patch 3 as:
> 
> if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp) &&
>     (DISPLAY_VER(display) < 35 ||
>      !intel_dp_tunnel_pr_optimization_supported(intel_dp)))
>

Sure, will add in intel_dp_tunnel_pr_optimization_supported().

Regards,
Animesh
 
> 	   BR,
> Jouni Högander
> 
> > +
> >  /**
> >   * intel_dp_tunnel_suspend - Suspend a DP tunnel connected on a port
> >   * @intel_dp: DP port object
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> > index 7f0f720e8dca..03e147736b65 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> > @@ -32,6 +32,7 @@ void intel_dp_tunnel_resume(struct intel_dp
> > *intel_dp,
> >  void intel_dp_tunnel_suspend(struct intel_dp *intel_dp);
> >
> >  bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp);
> > +bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp
> > *intel_dp);
> >
> >  void
> >  intel_dp_tunnel_atomic_cleanup_inherited_state(struct
> > intel_atomic_state *state);
> > @@ -76,6 +77,11 @@ static inline bool
> > intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp
> >  	return false;
> >  }
> >
> > +static inline bool intel_dp_tunnel_pr_optimization_supported(struct
> > intel_dp *intel_dp)
> > +{
> > +	return false;
> > +}
> > +
> >  static inline void
> >  intel_dp_tunnel_atomic_cleanup_inherited_state(struct
> > intel_atomic_state *state) {}
> >
> > diff --git a/include/drm/display/drm_dp_tunnel.h
> > b/include/drm/display/drm_dp_tunnel.h
> > index 87212c847915..4aa3ce9fd829 100644
> > --- a/include/drm/display/drm_dp_tunnel.h
> > +++ b/include/drm/display/drm_dp_tunnel.h
> > @@ -53,6 +53,7 @@ int drm_dp_tunnel_destroy(struct drm_dp_tunnel
> > *tunnel);
> >  int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel);
> >  int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel);
> >  bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel
> > *tunnel);
> > +bool drm_dp_tunnel_pr_optimization_supported(const struct
> > drm_dp_tunnel *tunnel);
> >  int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw);
> >  int drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel);
> >  int drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel); @@
> > -140,6 +141,11 @@ static inline bool
> > drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel
> >  	return false;
> >  }
> >
> > +static inline bool drm_dp_tunnel_pr_optimization_supported(const
> > struct drm_dp_tunnel *tunnel)
> > +{
> > +	return false;
> > +}
> > +
> >  static inline int
> >  drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw)
> >  {

Claude review: drm/i915/display: Add drm helper to check pr optimization support

[Claude Code Review Bot]

Patch Review

**Documentation typo:**
```
 * Returns %true if the PR BW optimiation is supported for @tunnel.
```
"optimiation" → "optimization"

**Redundancy with existing tree code:** The drm-next tree already reads `DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT` from `DP_TUNNELING_CAPABILITIES` in the `drm_dp_tunnel_detect()` debug print (line ~793 of `drm_dp_tunnel.c`), but doesn't store it. This patch correctly adds the `pr_optimization_support` bitfield and caches the value at tunnel creation time in `create_tunnel()`. However, note that `create_tunnel()` is called from `drm_dp_tunnel_detect()`, and the capability is already read from the same `regs` struct there. The approach is consistent with how `bw_alloc_supported` is handled — good.

**Missing update in `update_tunnel_regs()`:** The existing code checks whether `bw_alloc_supported` has changed across hotplug/resume in `update_tunnel_regs()` (around line 628). The new `pr_optimization_support` field is only set in `create_tunnel()` but is never updated or checked for changes in `update_tunnel_regs()`. If the tunnel bridge firmware were updated or the bridge changed, the cached value could become stale. Consider whether this needs a similar change-detection path. This is a minor concern since capability changes between detect calls are unlikely, but it's an inconsistency with the `bw_alloc_supported` pattern.

**No `EXPORT_SYMBOL_GPL`:** The existing exports in `drm_dp_tunnel.c` use `EXPORT_SYMBOL`. This patch follows the same convention, which is consistent. Just noting this is fine.

Overall this patch is clean and straightforward.

---
Generated by Claude Code Patch Reviewer

[PATCH v7 2/3] drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling

[Animesh Manna]

Unused bandwidth can be used by external display agents for Panel Replay
enabled DP panel during idleness with link on. Enable source to replace
dummy data from the display with data from another agent by programming
TRANS_DP2_CTL [Panel Replay Tunneling Enable].

v2:
- Enable pr bw optimization along with panel replay enable. [Jani]

v3:
- Write TRANS_DP2_CTL once for both bw optimization and panel replay
enable. [Jani]

v4:
- Read DPCD once in init() and store in panel_replay_caps. [Jouni]

v5:
- Avoid reading DPCD for edp. [Jouni]
- Use drm_dp_dpcd_read_byte() and some cosmetic changes. [Jani]

v6:
- Extend the corresponding interface defined in drm_dp_tunnel.c
to query the Panel Replay optimization capability. [Imre]

Bspec: 68920
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 24 +++++++++++++++++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 4746e9ebd920..dada8dc27ea4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2263,6 +2263,7 @@
 #define TRANS_DP2_CTL(trans)			_MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
 #define  TRANS_DP2_128B132B_CHANNEL_CODING	REG_BIT(31)
 #define  TRANS_DP2_PANEL_REPLAY_ENABLE		REG_BIT(30)
+#define  TRANS_DP2_PR_TUNNELING_ENABLE		REG_BIT(26)
 #define  TRANS_DP2_DEBUG_ENABLE			REG_BIT(23)
 
 #define _TRANS_DP2_VFREQHIGH_A			0x600a4
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5041a5a138d1..632527ede29f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -44,6 +44,7 @@
 #include "intel_dmc.h"
 #include "intel_dp.h"
 #include "intel_dp_aux.h"
+#include "intel_dp_tunnel.h"
 #include "intel_dsb.h"
 #include "intel_frontbuffer.h"
 #include "intel_hdmi.h"
@@ -1023,11 +1024,28 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp)
 	return frames_before_su_entry;
 }
 
+static bool intel_psr_allow_pr_bw_optimization(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	if (DISPLAY_VER(display) < 35)
+		return false;
+
+	if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+		return false;
+
+	if (!intel_dp_tunnel_pr_optimization_supported(intel_dp))
+		return false;
+
+	return true;
+}
+
 static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_psr *psr = &intel_dp->psr;
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
+	u32 dp2_ctl_val = TRANS_DP2_PANEL_REPLAY_ENABLE;
 
 	if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
 		u32 val = psr->su_region_et_enabled ?
@@ -1040,12 +1058,14 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
 			       val);
 	}
 
+	if (!intel_dp_is_edp(intel_dp) && intel_psr_allow_pr_bw_optimization(intel_dp))
+		dp2_ctl_val |= TRANS_DP2_PR_TUNNELING_ENABLE;
+
 	intel_de_rmw(display,
 		     PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),
 		     0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);
 
-	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
-		     TRANS_DP2_PANEL_REPLAY_ENABLE);
+	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, dp2_ctl_val);
 }
 
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
-- 
2.29.0

Re: [PATCH v7 2/3] drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling

[Hogander, Jouni]

On Thu, 2026-03-12 at 10:30 +0530, Animesh Manna wrote:
> Unused bandwidth can be used by external display agents for Panel
> Replay
> enabled DP panel during idleness with link on. Enable source to
> replace
> dummy data from the display with data from another agent by
> programming
> TRANS_DP2_CTL [Panel Replay Tunneling Enable].
> 
> v2:
> - Enable pr bw optimization along with panel replay enable. [Jani]
> 
> v3:
> - Write TRANS_DP2_CTL once for both bw optimization and panel replay
> enable. [Jani]
> 
> v4:
> - Read DPCD once in init() and store in panel_replay_caps. [Jouni]
> 
> v5:
> - Avoid reading DPCD for edp. [Jouni]
> - Use drm_dp_dpcd_read_byte() and some cosmetic changes. [Jani]
> 
> v6:
> - Extend the corresponding interface defined in drm_dp_tunnel.c
> to query the Panel Replay optimization capability. [Imre]
> 
> Bspec: 68920
> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_regs.h |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 24
> +++++++++++++++++--
>  2 files changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 4746e9ebd920..dada8dc27ea4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -2263,6 +2263,7 @@
>  #define TRANS_DP2_CTL(trans)			_MMIO_TRANS(trans,
> _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
>  #define  TRANS_DP2_128B132B_CHANNEL_CODING	REG_BIT(31)
>  #define  TRANS_DP2_PANEL_REPLAY_ENABLE		REG_BIT(30)
> +#define  TRANS_DP2_PR_TUNNELING_ENABLE		REG_BIT(26)
>  #define  TRANS_DP2_DEBUG_ENABLE			REG_BIT(23)
>  
>  #define _TRANS_DP2_VFREQHIGH_A			0x600a4
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5041a5a138d1..632527ede29f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -44,6 +44,7 @@
>  #include "intel_dmc.h"
>  #include "intel_dp.h"
>  #include "intel_dp_aux.h"
> +#include "intel_dp_tunnel.h"
>  #include "intel_dsb.h"
>  #include "intel_frontbuffer.h"
>  #include "intel_hdmi.h"
> @@ -1023,11 +1024,28 @@ static u8 frames_before_su_entry(struct
> intel_dp *intel_dp)
>  	return frames_before_su_entry;
>  }
>  
> +static bool intel_psr_allow_pr_bw_optimization(struct intel_dp
> *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	if (DISPLAY_VER(display) < 35)
> +		return false;

This is not necessary if you check it already at compute config.

> +
> +	if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
> +		return false;
> +
> +	if (!intel_dp_tunnel_pr_optimization_supported(intel_dp))
> +		return false;

You should move this patch after patch 3. Then you can drop this check.

> +
> +	return true;
> +}
> +
>  static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct intel_psr *psr = &intel_dp->psr;
>  	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> +	u32 dp2_ctl_val = TRANS_DP2_PANEL_REPLAY_ENABLE;
>  
>  	if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
>  		u32 val = psr->su_region_et_enabled ?
> @@ -1040,12 +1058,14 @@ static void dg2_activate_panel_replay(struct
> intel_dp *intel_dp)
>  			       val);
>  	}
>  
> +	if (!intel_dp_is_edp(intel_dp) &&
> intel_psr_allow_pr_bw_optimization(intel_dp))
> +		dp2_ctl_val |= TRANS_DP2_PR_TUNNELING_ENABLE;

If you do modification I commented above you could just check
intel_dp_tunnel_bw_alloc_is_enabled here. No need to add
intel_psr_allow_pr_bw_optimization helper.

BR,

Jouni Högander

>  		     PSR2_MAN_TRK_CTL(display, intel_dp-
> >psr.transcoder),
>  		     0,
> ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);
>  
> -	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp-
> >psr.transcoder), 0,
> -		     TRANS_DP2_PANEL_REPLAY_ENABLE);
> +	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp-
> >psr.transcoder), 0, dp2_ctl_val);
>  }
>  
>  static void hsw_activate_psr2(struct intel_dp *intel_dp)

RE: [PATCH v7 2/3] drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Thursday, March 12, 2026 12:15 PM
> To: intel-xe@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Manna,
> Animesh <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Deak, Imre <imre.deak@intel.com>
> Subject: Re: [PATCH v7 2/3] drm/i915/display: Panel Replay BW optimization
> for DP2.0 tunneling
> 
> On Thu, 2026-03-12 at 10:30 +0530, Animesh Manna wrote:
> > Unused bandwidth can be used by external display agents for Panel
> > Replay enabled DP panel during idleness with link on. Enable source to
> > replace dummy data from the display with data from another agent by
> > programming TRANS_DP2_CTL [Panel Replay Tunneling Enable].
> >
> > v2:
> > - Enable pr bw optimization along with panel replay enable. [Jani]
> >
> > v3:
> > - Write TRANS_DP2_CTL once for both bw optimization and panel replay
> > enable. [Jani]
> >
> > v4:
> > - Read DPCD once in init() and store in panel_replay_caps. [Jouni]
> >
> > v5:
> > - Avoid reading DPCD for edp. [Jouni]
> > - Use drm_dp_dpcd_read_byte() and some cosmetic changes. [Jani]
> >
> > v6:
> > - Extend the corresponding interface defined in drm_dp_tunnel.c to
> > query the Panel Replay optimization capability. [Imre]
> >
> > Bspec: 68920
> > Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_display_regs.h |  1 +
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 24
> > +++++++++++++++++--
> >  2 files changed, 23 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 4746e9ebd920..dada8dc27ea4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -2263,6 +2263,7 @@
> >  #define TRANS_DP2_CTL(trans)			_MMIO_TRANS(trans,
> > _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
> >  #define  TRANS_DP2_128B132B_CHANNEL_CODING	REG_BIT(31)
> >  #define  TRANS_DP2_PANEL_REPLAY_ENABLE		REG_BIT(30)
> > +#define  TRANS_DP2_PR_TUNNELING_ENABLE		REG_BIT(26)
> >  #define  TRANS_DP2_DEBUG_ENABLE			REG_BIT(23)
> >
> >  #define _TRANS_DP2_VFREQHIGH_A			0x600a4
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 5041a5a138d1..632527ede29f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -44,6 +44,7 @@
> >  #include "intel_dmc.h"
> >  #include "intel_dp.h"
> >  #include "intel_dp_aux.h"
> > +#include "intel_dp_tunnel.h"
> >  #include "intel_dsb.h"
> >  #include "intel_frontbuffer.h"
> >  #include "intel_hdmi.h"
> > @@ -1023,11 +1024,28 @@ static u8 frames_before_su_entry(struct
> > intel_dp *intel_dp)
> >  	return frames_before_su_entry;
> >  }
> >
> > +static bool intel_psr_allow_pr_bw_optimization(struct intel_dp
> > *intel_dp)
> > +{
> > +	struct intel_display *display = to_intel_display(intel_dp);
> > +
> > +	if (DISPLAY_VER(display) < 35)
> > +		return false;
> 
> This is not necessary if you check it already at compute config.
> 
> > +
> > +	if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
> > +		return false;
> > +
> > +	if (!intel_dp_tunnel_pr_optimization_supported(intel_dp))
> > +		return false;
> 
> You should move this patch after patch 3. Then you can drop this check.
> 
> > +
> > +	return true;
> > +}
> > +
> >  static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
> >  {
> >  	struct intel_display *display = to_intel_display(intel_dp);
> >  	struct intel_psr *psr = &intel_dp->psr;
> >  	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> > +	u32 dp2_ctl_val = TRANS_DP2_PANEL_REPLAY_ENABLE;
> >
> >  	if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
> >  		u32 val = psr->su_region_et_enabled ?
> > @@ -1040,12 +1058,14 @@ static void dg2_activate_panel_replay(struct
> > intel_dp *intel_dp)
> >  			       val);
> >  	}
> >
> > +	if (!intel_dp_is_edp(intel_dp) &&
> > intel_psr_allow_pr_bw_optimization(intel_dp))
> > +		dp2_ctl_val |= TRANS_DP2_PR_TUNNELING_ENABLE;
> 
> If you do modification I commented above you could just check
> intel_dp_tunnel_bw_alloc_is_enabled here. No need to add
> intel_psr_allow_pr_bw_optimization helper.

Sure, will check on this.

Regards,
Animesh
> 
> BR,
> 
> Jouni Högander
> 
> >  		     PSR2_MAN_TRK_CTL(display, intel_dp-
> > >psr.transcoder),
> >  		     0,
> > ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);
> >
> > -	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp-
> > >psr.transcoder), 0,
> > -		     TRANS_DP2_PANEL_REPLAY_ENABLE);
> > +	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp-
> > >psr.transcoder), 0, dp2_ctl_val);
> >  }
> >
> >  static void hsw_activate_psr2(struct intel_dp *intel_dp)

Claude review: drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling

[Claude Code Review Bot]

Patch Review

**Reviewed-by already present from Arun R Murthy.** 

**Register bit definition looks correct:** `TRANS_DP2_PR_TUNNELING_ENABLE` at `REG_BIT(26)` — fits between existing bit 30 (`PANEL_REPLAY_ENABLE`) and bit 23 (`DEBUG_ENABLE`), so the ordering in the header is correct.

**The `intel_psr_allow_pr_bw_optimization` check is clean:** It gates on DISPLAY_VER >= 35, bw_alloc being enabled, and PR optimization being supported. The DISPLAY_VER check is appropriate since this is a new hardware feature.

**Redundant `!intel_dp_is_edp()` check in `dg2_activate_panel_replay`:**
```c
if (!intel_dp_is_edp(intel_dp) && intel_psr_allow_pr_bw_optimization(intel_dp))
    dp2_ctl_val |= TRANS_DP2_PR_TUNNELING_ENABLE;
```
The `intel_psr_allow_pr_bw_optimization()` function already calls `intel_dp_tunnel_bw_alloc_is_enabled()` and `intel_dp_tunnel_pr_optimization_supported()`, which would both return false for eDP (no tunnel). The explicit `!intel_dp_is_edp()` check is technically redundant but serves as defensive documentation — acceptable.

**Missing deactivation/disable path:** When Panel Replay is deactivated, `TRANS_DP2_PR_TUNNELING_ENABLE` (bit 26) needs to be cleared. Looking at the existing code, `intel_psr_disable_locked()` calls `intel_de_rmw()` to clear `TRANS_DP2_PANEL_REPLAY_ENABLE` on the `TRANS_DP2_CTL` register. Does it also clear bit 26? I don't see the deactivation path being updated in this patch. If the existing disable code does `intel_de_rmw(display, TRANS_DP2_CTL(...), TRANS_DP2_PANEL_REPLAY_ENABLE, 0)`, then bit 26 would be left set after disable. This is a potential bug — the tunneling enable bit should be cleared when Panel Replay is disabled. Please verify the disable path clears `TRANS_DP2_PR_TUNNELING_ENABLE` as well.

**Copy-paste in wrapper doc comment (patch 1, but affects understanding):**
```c
 * Returns %true if the BW allocation mode is supported on @intel_dp.
```
This comment in `intel_dp_tunnel_pr_optimization_supported()` says "BW allocation mode" but should say "PR BW optimization". This is a copy-paste error from `intel_dp_tunnel_bw_alloc_is_enabled`.

---
Generated by Claude Code Patch Reviewer

[PATCH v7 3/3] drm/i915/display: Disable Panel Replay for DP-tunneling without optimization

[Animesh Manna]

As per DP specification,
    The DP Source device may optionally enable PR optimization
    with DP tunneling. The device shall query the Tunneling Bridge’s
    PR tunneling optimization capability by way of the
    Panel_Replay_Tunneling_Optimization_Support bit in the
    DP_TUNNELING_CAPABILITIES register (DPCD E000Dh[6]), and then enable PR
    only when the Tunneling Bridge is capable.

Therefore, do not enable Panel Replay for DP tunneling when optimization
support is not available.

Suggested-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 632527ede29f..3ec407a801b1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1796,6 +1796,13 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
 	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
 	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
 
+	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp) &&
+	    !intel_dp_tunnel_pr_optimization_supported(intel_dp)) {
+		drm_dbg_kms(display->drm,
+			    "Panel Replay is disabled as DP tunelling enabled without optimization\n");
+		return false;
+	}
+
 	if (!intel_dp_is_edp(intel_dp))
 		return true;
 
-- 
2.29.0

Re: [PATCH v7 3/3] drm/i915/display: Disable Panel Replay for DP-tunneling without optimization

[Hogander, Jouni]

On Thu, 2026-03-12 at 10:30 +0530, Animesh Manna wrote:
> As per DP specification,
>     The DP Source device may optionally enable PR optimization
>     with DP tunneling. The device shall query the Tunneling Bridge’s
>     PR tunneling optimization capability by way of the
>     Panel_Replay_Tunneling_Optimization_Support bit in the
>     DP_TUNNELING_CAPABILITIES register (DPCD E000Dh[6]), and then
> enable PR
>     only when the Tunneling Bridge is capable.
> 
> Therefore, do not enable Panel Replay for DP tunneling when
> optimization
> support is not available.
> 
> Suggested-by: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 632527ede29f..3ec407a801b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1796,6 +1796,13 @@ static bool
> _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
>  	crtc_state->link_off_after_as_sdp_when_pr_active =
> compute_link_off_after_as_sdp_when_pr_active(connector);
>  	crtc_state->disable_as_sdp_when_pr_active =
> compute_disable_as_sdp_when_pr_active(connector);
>  
> +	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp) &&
> +	    !intel_dp_tunnel_pr_optimization_supported(intel_dp)) {
> +		drm_dbg_kms(display->drm,
> +			    "Panel Replay is disabled as DP
> tunelling enabled without

typo tunelling vs. tunneling. How about:

"Panel Replay is disabled as DP tunnelling PR optimization not
supported."

?

BR,
Jouni Högander

> optimization\n");
> +		return false;
> +	}
> +
>  	if (!intel_dp_is_edp(intel_dp))
>  		return true;
>  

RE: [PATCH v7 3/3] drm/i915/display: Disable Panel Replay for DP-tunneling without optimization

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Thursday, March 12, 2026 11:48 AM
> To: intel-xe@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Manna,
> Animesh <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Deak, Imre <imre.deak@intel.com>
> Subject: Re: [PATCH v7 3/3] drm/i915/display: Disable Panel Replay for DP-
> tunneling without optimization
> 
> On Thu, 2026-03-12 at 10:30 +0530, Animesh Manna wrote:
> > As per DP specification,
> >     The DP Source device may optionally enable PR optimization
> >     with DP tunneling. The device shall query the Tunneling Bridge’s
> >     PR tunneling optimization capability by way of the
> >     Panel_Replay_Tunneling_Optimization_Support bit in the
> >     DP_TUNNELING_CAPABILITIES register (DPCD E000Dh[6]), and then
> > enable PR
> >     only when the Tunneling Bridge is capable.
> >
> > Therefore, do not enable Panel Replay for DP tunneling when
> > optimization support is not available.
> >
> > Suggested-by: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 632527ede29f..3ec407a801b1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1796,6 +1796,13 @@ static bool
> > _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
> >  	crtc_state->link_off_after_as_sdp_when_pr_active =
> > compute_link_off_after_as_sdp_when_pr_active(connector);
> >  	crtc_state->disable_as_sdp_when_pr_active =
> > compute_disable_as_sdp_when_pr_active(connector);
> >
> > +	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp) &&
> > +	    !intel_dp_tunnel_pr_optimization_supported(intel_dp)) {
> > +		drm_dbg_kms(display->drm,
> > +			    "Panel Replay is disabled as DP
> > tunelling enabled without
> 
> typo tunelling vs. tunneling. How about:
> 
> "Panel Replay is disabled as DP tunnelling PR optimization not supported."
> 
> ?
Sure, will modify in next version.

Regards,
Animesh
> 
> BR,
> Jouni Högander
> 
> > optimization\n");
> > +		return false;
> > +	}
> > +
> >  	if (!intel_dp_is_edp(intel_dp))
> >  		return true;
> >

Claude review: drm/i915/display: Disable Panel Replay for DP-tunneling without optimization

[Claude Code Review Bot]

Patch Review

**Typo in debug message:**
```c
"Panel Replay is disabled as DP tunelling enabled without optimization\n"
```
"tunelling" → "tunneling" (missing 'n').

**Placement of the check:** The check is inserted after computing `link_off_after_as_sdp_when_pr_active` and `disable_as_sdp_when_pr_active` but before the `!intel_dp_is_edp()` early return. This means these `crtc_state` fields get set even when Panel Replay will be disabled by this new check. Those fields are only meaningful when Panel Replay is active, so this is a minor inefficiency but not a bug — the state is ignored when `has_panel_replay` ends up false.

**The spec quote is helpful** — it clearly justifies why Panel Replay must be disabled when the bridge doesn't support PR tunneling optimization. Good commit message.

**Ordering concern between patch 2 and patch 3:** Patch 2 enables the optimization bit in the activation path, and patch 3 disables Panel Replay entirely when the optimization isn't supported. If patch 2 were applied alone (without patch 3), Panel Replay would still be enabled on tunneled connections without optimization support — just without the optimization bit set. The DP spec says PR should not be enabled in that case. Consider whether these should be reordered or squashed so there's no window where the driver violates the spec, even bisecting between patches.

**Summary of issues to address:**
1. **Typo** in patch 1 doc: "optimiation" → "optimization"
2. **Typo** in patch 3 debug message: "tunelling" → "tunneling"  
3. **Copy-paste error** in patch 1 `intel_dp_tunnel_pr_optimization_supported()` doc: says "BW allocation mode" instead of "PR BW optimization"
4. **Missing deactivation path** in patch 2: verify that `TRANS_DP2_PR_TUNNELING_ENABLE` is cleared when Panel Replay is disabled
5. **Patch ordering**: patch 3 should logically come before patch 2 to avoid a bisect-unsafe spec violation window
6. **Minor**: consider adding `pr_optimization_support` change detection in `update_tunnel_regs()` for consistency with `bw_alloc_supported`

---
Generated by Claude Code Patch Reviewer

Re: [PATCH v7 0/3] Panel Replay BW optimization

[Hogander, Jouni]

On Thu, 2026-03-12 at 10:30 +0530, Animesh Manna wrote:
> Unused bandwidth can be used by external display agents for Panel
> Replay
> enabled DP panel during idleness with link on. This patch series
> enabling the same.

Generic comment on this patch set. Maybe we should add one more patch
with "Fixes" tag:

Fixes: e60cff453b82 ("drm/i915/dp: Enable DP tunnel BW allocation
mode")
Cc: Imre Deak <imre.deak@intel.com>
Cc: <stable@vger.kernel.org> # v6.9+

This patch would just add:

if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) {
	drm_dbg_kms(display->drm,
		    "Panel Replay is disabled as DP tunneling
enabled\n");
	return false;
}

into _panel_replay_compute_config. this could be first patch in your
set. What do you think?

BR,
Jouni Högander

> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> 
> Animesh Manna (3):
>   drm/i915/display: Add drm helper to check pr optimization support
>   drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling
>   drm/i915/display: Disable Panel Replay for DP-tunneling without
>     optimization
> 
>  drivers/gpu/drm/display/drm_dp_tunnel.c       | 17 ++++++++++
>  .../gpu/drm/i915/display/intel_display_regs.h |  1 +
>  .../gpu/drm/i915/display/intel_dp_tunnel.c    | 14 +++++++++
>  .../gpu/drm/i915/display/intel_dp_tunnel.h    |  6 ++++
>  drivers/gpu/drm/i915/display/intel_psr.c      | 31
> +++++++++++++++++--
>  include/drm/display/drm_dp_tunnel.h           |  6 ++++
>  6 files changed, 73 insertions(+), 2 deletions(-)
> 

RE: [PATCH v7 0/3] Panel Replay BW optimization

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Thursday, March 12, 2026 1:36 PM
> To: intel-xe@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Manna,
> Animesh <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Deak, Imre <imre.deak@intel.com>
> Subject: Re: [PATCH v7 0/3] Panel Replay BW optimization
> 
> On Thu, 2026-03-12 at 10:30 +0530, Animesh Manna wrote:
> > Unused bandwidth can be used by external display agents for Panel
> > Replay enabled DP panel during idleness with link on. This patch
> > series enabling the same.
> 
> Generic comment on this patch set. Maybe we should add one more patch
> with "Fixes" tag:
> 
> Fixes: e60cff453b82 ("drm/i915/dp: Enable DP tunnel BW allocation
> mode")
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: <stable@vger.kernel.org> # v6.9+
> 
> This patch would just add:
> 
> if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) {
> 	drm_dbg_kms(display->drm,
> 		    "Panel Replay is disabled as DP tunneling enabled\n");
> 	return false;
> }
> 
> into _panel_replay_compute_config. this could be first patch in your set.
> What do you think?
Ok to me. Will take care in next version.

Regards,
Animesh
> 
> BR,
> Jouni Högander
> 
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >
> > Animesh Manna (3):
> >   drm/i915/display: Add drm helper to check pr optimization support
> >   drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling
> >   drm/i915/display: Disable Panel Replay for DP-tunneling without
> >     optimization
> >
> >  drivers/gpu/drm/display/drm_dp_tunnel.c       | 17 ++++++++++
> >  .../gpu/drm/i915/display/intel_display_regs.h |  1 +
> >  .../gpu/drm/i915/display/intel_dp_tunnel.c    | 14 +++++++++
> >  .../gpu/drm/i915/display/intel_dp_tunnel.h    |  6 ++++
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 31
> > +++++++++++++++++--
> >  include/drm/display/drm_dp_tunnel.h           |  6 ++++
> >  6 files changed, 73 insertions(+), 2 deletions(-)
> >

Re: [PATCH v7 0/3] Panel Replay BW optimization

[Imre Deak]

On Thu, Mar 12, 2026 at 10:05:35AM +0200, Hogander, Jouni wrote:
> On Thu, 2026-03-12 at 10:30 +0530, Animesh Manna wrote:
> > Unused bandwidth can be used by external display agents for Panel
> > Replay
> > enabled DP panel during idleness with link on. This patch series
> > enabling the same.
> 
> Generic comment on this patch set. Maybe we should add one more patch
> with "Fixes" tag:
> 
> Fixes: e60cff453b82 ("drm/i915/dp: Enable DP tunnel BW allocation mode")
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: <stable@vger.kernel.org> # v6.9+

Why? As I understand the Panel Replay BW optimization on a DP tunneled
link is an _optional_ feature, whereby the free BW can be used by the
Thunderbolt protocol for other purposes than for the given display
stream for which Panel Replay is enabled. IOW, it looks to me a valid
configuration to enable Panel Replay on a DP tunneled link without
enabling the Panel Replay BW optimization on it.

> This patch would just add:
> 
> if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) {
> 	drm_dbg_kms(display->drm,
> 		    "Panel Replay is disabled as DP tunneling enabled\n");
> 	return false;
> }
> 
> into _panel_replay_compute_config. this could be first patch in your
> set. What do you think?
> 
> BR,
> Jouni Högander
> 
> > 
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > 
> > Animesh Manna (3):
> >   drm/i915/display: Add drm helper to check pr optimization support
> >   drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling
> >   drm/i915/display: Disable Panel Replay for DP-tunneling without
> >     optimization
> > 
> >  drivers/gpu/drm/display/drm_dp_tunnel.c       | 17 ++++++++++
> >  .../gpu/drm/i915/display/intel_display_regs.h |  1 +
> >  .../gpu/drm/i915/display/intel_dp_tunnel.c    | 14 +++++++++
> >  .../gpu/drm/i915/display/intel_dp_tunnel.h    |  6 ++++
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 31
> > +++++++++++++++++--
> >  include/drm/display/drm_dp_tunnel.h           |  6 ++++
> >  6 files changed, 73 insertions(+), 2 deletions(-)
> > 
> 

Claude review: Panel Replay BW optimization

[Claude Code Review Bot]

Overall Series Review

Subject: Panel Replay BW optimization
Author: Animesh Manna <animesh.manna@intel.com>
Patches: 13
Reviewed: 2026-03-13T14:30:26.626654

---

This is a v7 3-patch series adding Panel Replay bandwidth optimization support for DP 2.0 tunneling in the i915 display driver. The concept is straightforward: when a Panel Replay-enabled DP panel is idle with the link on, unused bandwidth can be reclaimed by external display agents (e.g., USB4 data). The series adds infrastructure to query the tunnel bridge's capability, programs the hardware register bit to enable it, and disables Panel Replay entirely when tunneling is active but the bridge doesn't support the optimization (per DP spec requirement).

The series is generally clean and well-structured for a v7. A few issues noted below, ranging from a doc typo to a potential concern about deactivation path completeness.

---
Generated by Claude Code Patch Reviewer