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([2a01:e0a:106d:1080:8e54:fbaf:8cb6:e9f7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b5184962bsm16678526f8f.7.2026.03.19.07.54.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Mar 2026 07:54:07 -0700 (PDT) Message-ID: <3f8763af-aad2-4d92-90c8-cfd290212503@linaro.org> Date: Thu, 19 Mar 2026 15:54:06 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Subject: Re: [PATCH v3 4/4] drm/msm/dpu: fix video mode DSC INTF timing width calculation To: Alexander Koskovich Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Jeffrey Hugo , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org References: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> <20260319-dsi-rgb101010-support-v3-4-85b99df2d090@pm.me> <1360a31d-669e-48df-a1be-f0af4a253cd7@linaro.org> <3gLK4s97giqqXagfHKhfiIHbfbl2snwfOj9dcTNGPUYi10w9-1EdATqzz1LPCVTpz4bLFYOm8u_Fl8PfC7t5yabows4UCzRKVwjraEWW6hc=@pm.me> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 3/19/26 15:40, Alexander Koskovich wrote: > On Thursday, March 19th, 2026 at 10:13 AM, Neil Armstrong wrote: > >> Hi, >> >> On 3/19/26 12:58, Alexander Koskovich wrote: >>> Using bits_per_component * 3 as the divisor for the compressed INTF >>> timing width produces constant FIFO errors for the BOE BF068MWM-TD0 >>> panel due to bits_per_component being 10 which results in a divisor >>> of 30 instead of 24. >>> >>> Regardless of the compression ratio and pixel depth, 24 bits of >>> compressed data are transferred per pclk, so the divisor should >>> always be 24. >> >> Not true with widebus, specify why 24 and because DSI widebus is not implemented yet. >> >>> >>> Signed-off-by: Alexander Koskovich >>> --- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 ++++----- >>> 1 file changed, 4 insertions(+), 5 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> index 0ba777bda253..5419ef0be137 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> @@ -122,19 +122,18 @@ static void drm_mode_to_intf_timing_params( >>> } >>> >>> /* >>> - * for DSI, if compression is enabled, then divide the horizonal active >>> - * timing parameters by compression ratio. bits of 3 components(R/G/B) >>> - * is compressed into bits of 1 pixel. >>> + * For DSI, if DSC is enabled, 24 bits of compressed data are >>> + * transferred per pclk regardless of the source pixel depth. >>> */ >>> if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { >>> struct drm_dsc_config *dsc = >>> dpu_encoder_get_dsc_config(phys_enc->parent); >>> + >> Drop this change >> >>> /* >>> * TODO: replace drm_dsc_get_bpp_int with logic to handle >>> * fractional part if there is fraction >>> */ >>> - timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / >>> - (dsc->bits_per_component * 3); >>> + timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / 24; >> >> It would be helpful to somehow show that 24 is 8 * 3, 8 being the byte width and 3 the compression ratio. > > Can you clarify what the 3 represents? My panel should have a 3.75:1 compression > ratio (30/8) so the final divisor of 24 would be wrong for my panel if its the > compression ratio? So my guess is that while the exact ratio on the DSI lanes is 3.75:1, the ratio used to calculate the INTF timings is 3, then the DSC encoder probably does the magic to feed 10bpp into a 3.75:1 ratio over the DSI lanes. In dsi_adjust_pclk_for_compression, the pclk is adjusted to take in account bits_per_component, so I presume the actual DSI pclk _is_ timing->width * drm_dsc_get_bpp_int(dsc) / (dsc->bits_per_component * 3), which is your 3.75:1, but the INTF needs to generate timing->width * drm_dsc_get_bpp_int(dsc) / (8 * 3) pixels to the DSC encoder which will emit timing->width * drm_dsc_get_bpp_int(dsc) / (dsc->bits_per_component * 3) pixels. In any case, 24 _is_ 3 * 8, 3 being the DSC compression ratio on the INTF side. Dmitry, Konrad, could you help confirming this ? Neil > >> >>> timing->xres = timing->width; >>> } >>> } >>> >> >> >> > > Thanks, > Alex