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Fri, 15 May 2026 15:09:04 -0700 (PDT) X-Received: by 2002:a05:6a20:4305:b0:3a8:2339:24c4 with SMTP id adf61e73a8af0-3b22ebed4a2mr6668373637.26.1778882944158; Fri, 15 May 2026 15:09:04 -0700 (PDT) Received: from [192.168.1.3] ([182.60.13.113]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c82bb1156absm6447536a12.27.2026.05.15.15.08.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 May 2026 15:09:03 -0700 (PDT) Message-ID: <7d3dd8b9-8411-476d-a1ef-fdac476a1515@oss.qualcomm.com> Date: Sat, 16 May 2026 03:38:52 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/8] arm64: dts: qcom: Add GPU support for Kaanapali To: Konrad Dybcio Cc: Sean Paul , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter References: <20260512-kaana-gpu-dt-v1-0-13e1c07c2050@oss.qualcomm.com> <20260512-kaana-gpu-dt-v1-5-13e1c07c2050@oss.qualcomm.com> <14a2fbfd-97c1-4ba7-aa51-a07134102d3b@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <14a2fbfd-97c1-4ba7-aa51-a07134102d3b@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: biQg-Y4PIlT3XtAbCtTMVQi54rPupJMW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE1MDIyMSBTYWx0ZWRfX60i12QGDytt9 XRbZrDr8wyG8gWKL+SBf5q31flGbEXdTpvU2RkDtoVc78SIorGl5ZKO2wHVPNWNt003fiyhtT2T byzsbmECCzBFlcLSKD6Y8KARUIg3Ofvyh+iP2NQXG/iSGDUsilLNHhM7SVirgzaCyfz+CZgrGFH 6Z41wNJeEqE2FqU0Vu60JAWgkE4rl4GtmmiaFATGuJVmMTdAMyGihsHaAMDEEeDvGW51gQi/OjE jFMle1c3xnBwYsU/anNCurisUeKqMFJpsuBqzXG2XtLpc7RAJMbwoR62H0dmsoXG8a6M4zGhsp2 hZUjP1yNTCj9Z9cLqtvGS/0mmc9QX2gc3aD0emOxd78WiRAl6GH2voB7FuLV/bj6Kbq4viw6bMN S0gfFrzC0b8A6lqr1oWoLJa6Ik6kGi9/+45PpxtzubUpwY+ALUYfZLMqm0z6qjYmeYVe+n74as6 LiX7jdCFhf3vJdRa56Q== X-Authority-Analysis: v=2.4 cv=E9f9Y6dl c=1 sm=1 tr=0 ts=6a079981 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ba8plz+5YpscmDk5DVa2Cg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=mzNi1YEEKYKHT8R6ei4A:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: biQg-Y4PIlT3XtAbCtTMVQi54rPupJMW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-15_05,2026-05-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 malwarescore=0 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605150221 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 5/14/2026 6:13 PM, Konrad Dybcio wrote: > On 5/12/26 12:23 AM, Akhil P Oommen wrote: >> Adreno 840 present in Kaanapali SoC is the second generation GPU in >> A8x family. It is based on the new slice architecture with 3 slices, >> higher GMEM/caches etc. >> >> There is some re-arrangement in the reglist to properly cover maximum >> register region. Other than this, the DT description is mostly similar >> to the existing chipsets except the OPP tables. >> >> Signed-off-by: Akhil P Oommen >> --- > > [...] > >> + gpu_opp_table: opp-table { >> + compatible = "operating-points-v2-adreno", >> + "operating-points-v2"; >> + >> + opp-222000000 { >> + opp-hz = /bits/ 64 <222000000>; >> + opp-level = ; >> + opp-peak-kBps = <2136718>; >> + opp-supported-hw = <0x0f>; >> + /* ACD is disabled */ >> + }; > > The clock plan also has a 160 MHz OPP @ LOWSVS_D3 and there's a couple of > interim OPPs that you have that aren't part of it (but maybe you have > better docs) I somehow assumed that the 160Mhz was a thermal-only corner. Seems it is not. Let me revisit the OPP table again. Yeah, the doc is outdated. Looks like there was some last minute updates to the OPP table. Also, we should update a6xx_hfi.h to accommodate more than 16 GX levels. -Akhil. > > Otherwise lgtm but the size of the GPU region and the GMU base look > slightly confusing when I'm comparing them against the reg map > > Konrad